Senior ASIC Design Verification Engineer

Nvidia

Confirmed live today Trusted

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Employment: Full-time
Posted: 92 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Similar $192k

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Engineer

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The Senior ASIC Design Verification Engineer joins the Circuit Solutions Group to drive sign-off strategies for GPUs and SoCs. This role involves owning unit and sub-system level verification for innovative IPs covering hardware security, clocking, voltage regulation, and silicon correlation. Key responsibilities include creating functional test plans, building verification infrastructure, and participating in design specification development for architecture and implementation. The engineer will also develop and deploy agentic AI frameworks for DV workflows like stimulus generation and regression triage. Required technical skills include proficiency in Object Oriented Programming, Verilog, SystemVerilog, UVM, SVA, and functional coverage development using VCS or Questa. Candidates should also possess debugging skills, knowledge of behavioral real number modeling, and experience with co-simulation environments like VCS-XA or Formal Equivalence domains.

Skills

System Verilog UVM Verilog SVA VCS Questa Perl Tcl Make Formal Equivalence Gate Level Simulation LLMs Agentic AI Functional Coverage Mixed Signal Design Co-simulation ASIC Design Verification

What you'll do

Develop innovative IPs for hardware security, clocking, voltage regulation, and silicon correlation.
Own unit and sub-system level verification for various IPs using advanced verification tools and methodologies.
Create comprehensive functional test plans to verify IP designs.
Build and reform world-class verification infrastructure and methodologies for custom designed IPs.
Participate in design specification development by discussing architecture, intent, and implementation.
Enable system-level integration by developing test plans, debugging, and delivering Verification IPs.
Develop and deploy agentic AI frameworks for stimulus generation, regression triage, and root cause analysis.

What we're looking for

BSEE with 5+ years of experience in unit or sub-system level verification.
MS in Electrical or Computer Engineering with 3+ years of experience in unit or sub-system level verification (preferred).
Proficiency in Object Oriented Programming, Verilog, SystemVerilog, UVM, SVA, and functional coverage development.
Strong skills with VCS or equivalent simulation tools like Questa.
Strong debugging and analytical skills.
Proficiency in developing and implementing agentic AI workflows using LLMs and industry standard frameworks (preferred).
Knowledge of custom designed IPs with understanding of behavioral real number modeling of low level digital or mixed signal designs (preferred).
Knowledge of co-simulation environments, Gate Level Simulation, or Formal Equivalence domains (preferred).

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