Senior ASIC Design Verification Engineer

Nvidia

Confirmed live yesterday Trusted

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $136,000–$218,500 / yr
Posted: 46 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k

This role $177k

$126k most similar roles pay here $230k

This role pays less than 54% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Engineer

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As a Senior ASIC Design Verification Engineer within the Circuit Solutions Group, you will drive sign-off strategies for GPUs and SoCs while developing innovative IPs for hardware security, clocking, voltage regulation, and silicon correlation. You will own unit and sub-system level verification, create functional test plans, and build world-class verification infrastructure to meet custom design demands. Your daily work involves engaging in architecture discussions, collaborating with partner teams on system integration, and deploying agentic AI frameworks for DV workflows like stimulus generation and regression triage. Required skills include proficiency in Verilog, SystemVerilog, UVM, SVA, and Object Oriented Programming, alongside experience with VCS or Questa tools. You will also utilize scripting languages like Perl and Tcl to automate processes while ensuring bug-free first silicon across complex hardware domains.

Skills

System Verilog UVM SVA Verilog VCS Questa Perl Tcl Make files Gate Level Simulation Formal Equivalence LLMs Agentic AI Frameworks Mixed Signal Design Functional Coverage Co-simulation

What you'll do

Own unit and sub-system level verification for hardware security, clocking, and voltage regulation IPs.
Create functional test plans and verify designs using advanced verification tools, flows, and methodologies.
Build and reform world-class verification infrastructure to meet the demands of custom designed IPs.
Participate in design specification discussions regarding architecture, intent, and implementation of various IPs.
Collaborate with partner teams to develop test suites and deliver functional Verification IPs for system integration.
Develop and deploy agentic AI frameworks for DV workflows including stimulus generation and regression triage.
Perform root cause analysis and debug complex issues to ensure bug-free first silicon.

What we're looking for

A BSEE degree is required with at least 5 years of experience in unit or sub-system level verification.
An MS in Electrical or Computer Engineering is accepted with at least 3 years of experience in unit or sub-system level verification.
Proficiency in Verilog, SystemVerilog, UVM, SVA, and functional coverage development is required.
Proficiency in Object Oriented Programming is required.
Experience with VCS or equivalent simulation tools like Questa is required.
Strong debugging and analytical skills are required.
Proficiency in scripting languages such as Perl, Tcl, Make files, and automation methods is preferred.
Experience with agentic AI workflows using LLMs and standard frameworks is a plus.

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