Senior ASIC Design Verification Engineer

What you'll do

• Own unit and sub-system level verification of IPs, creating functional test plans and using advanced verification tools.
• Develop innovative hardware security, clocking, voltage regulation IPs for custom designed solutions.
• Build world-class verification infrastructure and methodologies to meet unique demands of custom IPs.
• Engage in design specification development by participating in discussions on architecture and implementation of IPs.
• Enable system level integration by working with partner teams for test development and delivering Verification IPs.

What we're looking for

• BSEE (or equivalent) with 5+ years of ASIC verification experience or MS with 3+ years.
• Expertise in Verilog, SystemVerilog, UVM, SVA, and functional coverage development.
• Proficiency in VCS simulation tools and agentic AI frameworks for DV workflows.
• Strong debugging skills and continuous improvement mindset focused on bug-free silicon.
• Knowledge of custom IP solutions, co-simulation environments, and gate-level simulation.