ASIC Design Verification Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Irvine, CAAndover, MABroomfield, CO
Salary: $129,400–$207,000 / yr
Employment: Full-time
Posted: 132 days ago
Freshness: Confirmed live today
Closes: Dec 12, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $190k

This role $168k

$118k $237k

below market most similar roles pay here above market

This role pays less than 71% of similar roles. Most pay $162,000–$217,525 — the blue band above. At the midpoint, this role pays about $168k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

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The ASIC Design Verification Engineer joins a stable team developing silicon products for Ethernet systems in the Cloud to accelerate AI/ML workflows. This role focuses on creating high throughput Ethernet solutions that deliver performance and power efficiency. The engineer will work with worldwide design and architecture teams to verify new designs that evolve rapidly across generations. Key responsibilities include performing all aspects of Design Verification and providing technical leadership. The candidate must utilize constrained random verification methodologies to drive completion via coverage closure. Required technical skills include System Verilog and UVM, with specific experience in TB structures, Class, and SVA. Proficiency with VCS, Incisive, and scripting languages like Python or Perl is also required to solve complex technical problems within this dynamic market.

Skills

System Verilog UVM Constrained Random Verification VCS Incisive Python Perl OOP SVA Coverage Closure Ethernet AI/ML Scripting

What you'll do

Verify new silicon designs for high-throughput Ethernet solutions using SystemVerilog and UVM.
Develop constrained random verification methodologies to ensure design accuracy.
Drive verification completion through rigorous coverage closure.
Build testbench structures using Object-Oriented Programming (OOP) principles.
Utilize industry-standard tools including VCS and Incisive for verification tasks.
Write scripts in Python or Perl to automate verification processes.
Provide technical leadership on all aspects of the Design Verification lifecycle.

What we're looking for

Bachelors degree and 12+ years of related experience.
Masters degree and 10+ years of related experience.
PhD and 3+ years of related experience.
Experience with constrained random verification methodologies and driving completion via coverage closure.
Skills with SystemVerilog and UVM (preferred).
Proficiency with SystemVerilog tools including Class, SVA, VCS, and Incisive (preferred).
Scripting skills in languages such as Python or Perl (preferred).
Strong sense of teamwork and a self-motivated personality.

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