Senior ASIC Design Verification Engineer

Nvidia

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CAWestford, MAAustin, TXDurham, NCBoulder, COSeattle, WA
Salary
$168,000–$264,500 / yr
Posted
2 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $195k
This role $216k
$137k most similar roles pay here $278k

This role pays more than 76% of similar roles. Most pay $174,375–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 879 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 859 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Engineer

As a Senior ASIC Design Verification Engineer - LPU, you will join the ASIC Verification team to verify the design and implementation of a leading inference accelerator. You will be responsible for verifying the ASIC design, architecture, reference models, and micro-architecture using advanced verification methodologies while defining the verification scope and developing infrastructure. Your daily work involves collaborating with architects and designers, implementing automated verification flows, and ensuring the correctness of high-performance processor elements that provide programmable compute and graphics functionality. You will utilize SystemVerilog, Universal Verification Methodology (UVM), and tools like VCS or Verdi. The role requires expertise in random stimulus, functional coverage, and assertion-based methodologies. Additional experience with UPF power verification, netlist and DFT verification, and programming in Perl, Python, or C/C++ is highly valued for this inference accelerator project.

What you'll do

  • Verify the design and implementation of inference accelerator hardware.
  • Verify ASIC designs, architectures, reference models, and micro-architecture using advanced methodologies.
  • Define verification scope and develop necessary verification infrastructure for assigned units.
  • Implement and optimize automated verification flows to improve team productivity and efficiency.
  • Utilize SystemVerilog and Universal Verification Methodology (UVM) to ensure design correctness.
  • Apply random stimulus, functional coverage, and assertion-based verification techniques.
  • Incorporate innovative techniques and latest trends into the ASIC design verification process.

What we're looking for

  • Bachelor's Degree in EE, CS, or CE (or equivalent experience).
  • 8+ years of relevant industry experience.
  • Experience building block and SoC level testbenches with strong debugging and analytical skills.
  • Experience using random stimulus, functional coverage, and assertion-based verification methodologies and tools.
  • Expertise in SystemVerilog and Universal Verification Methodology (UVM).
  • Experience with design and verification tools such as VCS or Verdi.
  • Background in UPF power verification (preferred).
  • Experience in netlist and DFT verification (preferred).

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