Senior Design Verification Engineer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$115,600–$173,400 / yr
Posted
21 days ago
Freshness
Confirmed live yesterday
Closes
Feb 17, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k
This role $144k
$103k most similar roles pay here $231k

This role pays less than 88% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $144k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Senior Design Verification Engineer

ASICS Design Verification Engineer-Senior joins the ASICS Engineering team to manage the complete verification lifecycle from system-level concept through tape out and post-silicon support. The role focuses on comprehensive pre-silicon test planning for digital power IP, where the engineer will develop testbenches, coverage models, assertion models, and formal verification property checking. Additionally, the position involves deploying power-aware UPF verification flows and developing automation to improve overall efficiency. Key technical requirements include proficiency in SystemVerilog, UVM, Verilog, VHDL, and C or C++ programming. Candidates should possess skills in Perl or Python scripting and knowledge of AMBA Bus protocols like AXI, AHB, and APB. The work centers on solving complex verification challenges for digital power IP within the semiconductor space to ensure robust hardware functionality before production.

What you'll do

  • Perform comprehensive pre-silicon test planning for digital power IPs.
  • Develop testbenches using advanced verification methodologies such as SystemVerilog and UVM.
  • Create coverage models and assertion models to ensure design integrity.
  • Execute formal verification through property checking.
  • Deploy power-aware UPF verification flows and methodologies.
  • Develop automation tools to improve overall verification efficiency.
  • Support the complete verification lifecycle from system-level concept to post-silicon support.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field (or Master's with 1+ year experience, or PhD).
  • 2+ years of experience with ASIC design and verification tools, techniques, and methodology.
  • Master’s degree in Computer Science, Electrical Engineering, or Computer Engineering (preferred).
  • 6+ years of experience with ASIC design and verification tools, techniques, and methodology (preferred).
  • 6+ years of experience with digital design concepts and RTL languages such as SystemVerilog, Verilog, or VHDL (preferred).
  • 6+ years of experience with computer architecture fundamentals, OOP concepts, and C or C++ programming skills (preferred).
  • 6+ years of experience with SystemVerilog testbench development, UVM/OVM methodologies, and scripting in Perl or Python (preferred).
  • Experience with AMBA Bus protocols and Assertion Based Formal Verification (preferred).

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