ASIC Design Verification Engineer

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$107,400–$161,200 / yr
Posted
23 days ago
Freshness
Confirmed live yesterday
Closes
Feb 15, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $188k
This role $134k
$94k most similar roles pay here $234k

This role pays less than 92% of similar roles. Most pay $162,000–$214,000 — the shaded band above. At the midpoint, this role pays about $134k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

As an ASIC Design Verification Engineer within the ASICS Engineering group, you will manage the complete verification lifecycle from system-level concept to tape out and post-silicon support. You will perform comprehensive pre-silicon test planning for digital power IPs, develop testbenches using SystemVerilog-UVM, create coverage and assertion models, and utilize formal verification property checking. Your daily work involves deploying power-aware UPF verification flows and developing automation to improve efficiency. The role requires expertise in SystemVerilog, UVM, C++, and Python while addressing complex SoC subsystems, caches, and DDR memory protocols. You will also handle performance and power verification, PASIM simulations, and firmware or driver development. This position focuses on the technical challenges of verifying sophisticated hardware components and ensuring robust functionality across various integrated circuits before they reach final production stages.

What you'll do

  • Perform comprehensive pre-silicon test planning for digital power IPs.
  • Develop testbenches using SystemVerilog and UVM methodologies.
  • Create coverage models and assertion models for verification.
  • Execute formal verification and property checking.
  • Deploy power-aware UPF verification flows and methodologies.
  • Develop automation tools to improve verification efficiency.
  • Perform performance and power verification for SoC subsystems.
  • Support the full lifecycle from system-level concept to post-silicon debug.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field.
  • Minimum 3 years of DV experience using UVM and assertion-based verification technologies.
  • Experience verifying complex SOCs or SOC subsystems.
  • Experience with cache and DDR memory protocol verification.
  • Experience using memory verification VIPs.
  • Exposure to DDR PHY, formal verification, PASIM simulations, and performance/power verification.
  • Exposure to firmware/driver development using C++.
  • Exposure to multiple successful tapeouts from conception to post-silicon debug.

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