ASIC Design Verification Engineer
Qualcomm
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How this pay compares to similar roles
This role pays less than 91% of similar roles. Most pay $162,000–$216,562 — the blue band above. At the midpoint, this role pays about $141k versus about $189k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 575 open roles on FindRole.
Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.
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ASIC Design Verification Engineer The ASIC Design Verification Engineer joins the ASICS Engineering group to manage the complete verification lifecycle from system-level concept to tape out and post-silicon support. The role involves comprehensive pre-silicon test planning for digital power IPs, including testbench development using SystemVerilog-UVM, coverage development, assertion model development, and formal verification property checking. Key responsibilities include deploying power-aware UPF verification flows and developing automation to improve verification efficiency. Candidates must utilize SystemVerilog, UVM, C++, and Python to verify complex SOC subsystems, caches, and DDR memory protocols. The work requires experience with memory verification VIPs, DDR phy, PASIM simulations, and performance and power verification to ensure robust hardware functionality across various digital power IP components throughout the design process.
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