ASIC Design Verification Engineer
Qualcomm
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How this pay compares to similar roles
This role pays less than 92% of similar roles. Most pay $162,000–$214,000 — the shaded band above. At the midpoint, this role pays about $134k versus about $188k for comparable roles.
Based on 240 similar postings.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 623 open roles on FindRole.
Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.
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At a glance
As an ASIC Design Verification Engineer within the ASICS Engineering group, you will manage the complete verification lifecycle from system-level concept to tape out and post-silicon support. You will perform comprehensive pre-silicon test planning for digital power IPs, develop testbenches using SystemVerilog-UVM, create coverage and assertion models, and utilize formal verification property checking. Your daily work involves deploying power-aware UPF verification flows and developing automation to improve efficiency. The role requires expertise in SystemVerilog, UVM, C++, and Python while addressing complex SoC subsystems, caches, and DDR memory protocols. You will also handle performance and power verification, PASIM simulations, and firmware or driver development. This position focuses on the technical challenges of verifying sophisticated hardware components and ensuring robust functionality across various integrated circuits before they reach final production stages.
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