ASIC Design Verification Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$113,000–$169,600 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k
This role $141k
$100k $239k
below market most similar roles pay here above market

This role pays less than 91% of similar roles. Most pay $162,000–$216,562 — the blue band above. At the midpoint, this role pays about $141k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

ASIC Design Verification Engineer The ASIC Design Verification Engineer joins the ASICS Engineering group to manage the complete verification lifecycle from system-level concept to tape out and post-silicon support. The role involves comprehensive pre-silicon test planning for digital power IPs, including testbench development using SystemVerilog-UVM, coverage development, assertion model development, and formal verification property checking. Key responsibilities include deploying power-aware UPF verification flows and developing automation to improve verification efficiency. Candidates must utilize SystemVerilog, UVM, C++, and Python to verify complex SOC subsystems, caches, and DDR memory protocols. The work requires experience with memory verification VIPs, DDR phy, PASIM simulations, and performance and power verification to ensure robust hardware functionality across various digital power IP components throughout the design process.

What you'll do

  • Perform comprehensive pre-silicon test planning for digital power IPs.
  • Develop testbenches using SystemVerilog-UVM and advanced verification methodologies.
  • Create coverage models and assertion models for design verification.
  • Execute formal verification and property checking for complex SOC subsystems.
  • Deploy and manage power-aware UPF verification flows and methodologies.
  • Develop automation tools to improve overall verification efficiency.
  • Conduct performance and power verification for various hardware components.
  • Support the full verification lifecycle from system-level concept to post-silicon debug.

What we're looking for

  • Bachelor's degree in Science, Engineering, or a related field.
  • Minimum 3 years of DV experience using UVM and assertion-based verification technologies.
  • Experience verifying complex SOCs or SOC subsystems.
  • Experience with caches and DDR memory protocol verification.
  • Experience using memory verification VIPs.
  • Exposure to DDR phy.
  • Exposure to firmware/driver development using C++.
  • Exposure to multiple successful tapeouts from conception to post-silicon debug.

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