Browse tech roles

ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP +15 more Show less

System Verilog UVM Python Perl ASIC Gate Level Simulation Veloce Palladium Zebu HAPS P4 PCIe CXL Ethernet RDMA DDR TCP Formal Verification +13 more Show less

System Verilog UVM Constrained Random Verification VCS Incisive Python Perl SVA OOP Coverage Closure Ethernet AI/ML Scripting +8 more Show less

System Verilog UVM Python Perl ASIC Design Verification Gate Level Simulation Veloce Palladium Zebu HAPS VC Formal IEV P4 PCIe CXL Ethernet RDMA DDR TCP +14 more Show less

UVM System C C++ C Matlab Formal Verification DPI-C RTL FPGA Emulation DSP Scripting +7 more Show less

SystemVerilog UVM ASIC Verification Python Perl FPGA Cadence Palladium Siemens Veloce Synopsys ZeBu PCIe Ethernet CXL HBM DDR SoC Architecture Silicon Bring-up Post-Silicon Validation Regression Infrastructure +13 more Show less

UVM C/C++ Formal Verification Matlab System C DPI-C RTL FPGA Emulation Scripting DSP CMOS +7 more Show less

SystemVerilog UVM ASIC Verification Python C/C++ Perl VCS Verdi DFT UPF Machine Learning SoC Functional Coverage Assertion-based Verification GDS +10 more Show less

SystemVerilog UVM assertion based verification C++ Python Formal Verification UPF DDR SOC Cache post silicon debug PASIM Power Verification +8 more Show less

SystemVerilog UVM Verilog VHDL Python C++ C Perl Formal Verification UPF AMBA AXI AHB APB ASIC Design RTL Object-oriented programming Automation +13 more Show less

SystemVerilog UVM C++ Python Formal Verification assertion based verification UPF DDR SOC Cache post silicon debug PASIM Power Verification +8 more Show less

SystemVerilog UVM RTL ASIC Mixed-Signal Verification Real-Number Modeling RNM Verilog-AMS SVA Formal Verification Co-simulation FPGA Prototyping Regression Automation Post-silicon Bring-up Hardware/Software Co-verification +10 more Show less

ASIC SystemVerilog Verilog UVM Python Perl VCS Verdi Xcelium RTL Pre-silicon Verification infrastructure, automation Simulation Debug Root-cause Analysis +10 more Show less

System Verilog UVM Verilog SVA VCS Questa Perl Tcl Make Formal Equivalence Gate Level Simulation LLMs Agentic AI Functional Coverage Mixed Signal Design Co-simulation ASIC Design Verification +12 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models Scripting Digital Design +10 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage Test Plans Scripting +10 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage +8 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage Test Plans Scripting +10 more Show less

SystemVerilog UVM Verilog SystemC Matlab C DPI-C Formal Verification RTL DSP CMOS Scripting +7 more Show less

UVM C/C++ Formal Verification System C DPI-C Matlab RTL FPGA Emulation Scripting DSP CMOS +7 more Show less