ASIC Design Verification Technical Leader

Cisco

Confirmed live 2 days ago Trusted

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $186,900–$267,700 / yr
Posted: 22 days ago
Freshness: Confirmed live 2 days ago
Closes: Oct 20, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k

This role $227k

$133k most similar roles pay here $282k

This role pays more than 78% of similar roles. Most pay $168,500–$223,175 — the shaded band above. At the midpoint, this role pays about $227k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Technical Leader

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As an ASIC Design Verification Technical Leader within the Common Hardware Group, you will lead the planning and execution of verification for complex networking SoCs. You will drive verification strategy, testplan development, coverage closure, and infrastructure improvements while providing technical leadership and mentorship to engineers. Your daily work involves developing scalable, reusable environments and collaborating with architecture, RTL, emulation, FPGA, and post-silicon teams to ensure successful silicon bring-up and root cause analysis. The role requires expertise in SystemVerilog, UVM, and modern verification methodologies including hardware emulation on platforms like Cadence Palladium or Synopsys ZeBu. You will also utilize scripting languages such as Python or Perl. This position focuses on the technical challenges of high-speed protocols like PCIe, Ethernet, CXL, HBM, and DDR within large-scale SoC architectures for networking products.

Skills

SystemVerilog UVM ASIC Verification Python Perl Hardware Emulation FPGA Cadence Palladium Siemens Veloce Synopsys ZeBu PCIe Ethernet CXL HBM DDR RTL Silicon Bring-up Post-Silicon Validation

What you'll do

Lead the planning and execution of ASIC verification for complex networking SoCs.
Drive verification strategy, testplan development, coverage closure, and execution across multiple IPs.
Develop and enhance scalable, reusable verification environments and infrastructure using SystemVerilog/UVM.
Provide technical leadership and mentorship to verification engineers to promote best practices.
Lead complex debug efforts and perform root cause analysis across simulation, emulation, and silicon.
Collaborate with architecture, RTL, emulation, FPGA, and post-silicon teams for successful silicon bring-up.
Champion improvements in verification productivity, automation, regression efficiency, and quality metrics.
Evaluate and adopt new verification technologies and industry best practices to improve effectiveness.

What we're looking for

Bachelor's degree with 10+ years of experience, Master's with 7+ years, or Ph.D. with 5+ years of related experience.
Strong experience with SystemVerilog, UVM, and modern verification methodologies including hardware emulation.
Experience developing and executing verification strategies for complex ASIC or SoC programs.
Experience leading verification teams or serving as the technical lead for complex verification projects.
Proficiency in scripting languages such as Python or Perl.
Experience with Datacenter, Hyperscaler, AI, or networking ASICs (preferred).
Deep understanding of high-speed protocols like PCIe, Ethernet, CXL, HBM, and DDR and large-scale SoC architectures (preferred).
Hands-on experience with hardware emulation platforms, silicon bring-up, post-silicon validation, and debug (preferred).

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