ASIC Design Verification Technical Leader

Cisco

Confirmed live today High trust
Closes tomorrow

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
29 days ago
Freshness
Confirmed live today
Closes
Oct 28, 2026 (soon)

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k
This role $227k
$136k $282k
below market most similar roles pay here above market

This role pays more than 77% of similar roles. Most pay $168,200–$227,300 — the blue band above. At the midpoint, this role pays about $227k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Technical Leader

The ASIC Design Verification Technical Leader joins the Common Hardware Group to lead the planning and execution of ASIC verification for complex networking SoCs. This role involves driving verification strategy, testplan development, and coverage closure across multiple IPs and subsystem-level efforts. You will provide technical leadership and mentorship to verification engineers while developing scalable, reusable verification environments and infrastructure. Key responsibilities include performing root cause analysis, leading complex debug efforts, and championing improvements in regression efficiency and automation. The position requires proficiency in SystemVerilog, UVM, and scripting languages like Python or Perl. Candidates must possess experience with hardware emulation platforms such as Cadence Palladium or Synopsys ZeBu. The work focuses on solving technical challenges within high-speed protocols like PCIe, Ethernet, CXL, HBM, and DDR for networking hardware.

What you'll do

  • Lead the planning and execution of ASIC verification for complex networking SoCs.
  • Drive verification strategy, testplan development, coverage closure, and execution across multiple IPs.
  • Develop and enhance scalable, reusable verification environments and methodologies using SystemVerilog/UVM.
  • Provide technical leadership and mentorship to verification engineers to promote best practices.
  • Lead complex debug efforts and perform root cause analysis across simulation, emulation, and silicon.
  • Champion continuous improvements in verification productivity, automation, and regression efficiency.
  • Evaluate and adopt new verification technologies and industry best practices to improve effectiveness.

What we're looking for

  • Bachelor's degree with 10+ years of related experience, Master's degree with 7+ years, or Ph.D. with 5+ years of related experience.
  • Strong experience with SystemVerilog, UVM, and modern verification methodologies, including hardware emulation.
  • Experience developing and executing verification strategies for complex ASIC or SoC programs.
  • Experience leading verification teams or serving as the technical lead for complex verification projects.
  • Proficiency in scripting languages such as Python or Perl.
  • Experience with Datacenter, Hyperscaler, AI, or networking ASICs (preferred).
  • Deep understanding of high-speed protocols like PCIe, Ethernet, CXL, HBM, and DDR (preferred).
  • Hands-on experience with hardware emulation platforms such as FPGA prototyping, Palladium, Veloce, or ZeBu (preferred).

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