ASIC Design Verification Engineer
Cisco
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How this pay compares to similar roles
This role pays more than 77% of similar roles. Most pay $168,200–$227,300 — the blue band above. At the midpoint, this role pays about $227k versus about $198k for comparable roles.
Based on 240 similar postings.
Employer
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has 307 open roles on FindRole.
Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.
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At a glance
The ASIC Design Verification Technical Leader joins the Common Hardware Group to lead the planning and execution of ASIC verification for complex networking SoCs. This role involves driving verification strategy, testplan development, and coverage closure across multiple IPs and subsystem-level efforts. You will provide technical leadership and mentorship to verification engineers while developing scalable, reusable verification environments and infrastructure. Key responsibilities include performing root cause analysis, leading complex debug efforts, and championing improvements in regression efficiency and automation. The position requires proficiency in SystemVerilog, UVM, and scripting languages like Python or Perl. Candidates must possess experience with hardware emulation platforms such as Cadence Palladium or Synopsys ZeBu. The work focuses on solving technical challenges within high-speed protocols like PCIe, Ethernet, CXL, HBM, and DDR for networking hardware.
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