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Active Keyword: ASIC Design Engineer Remove filter Location: Sunnyvale Remove filter Clear all

18 of up to 20 (filtered)

ASIC Design Engineer, Pixel IP

Apple Inc

Sunnyvale, CA 9 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
RTL Design AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification ASIC Design
10+ yrs exp
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ASIC Design Engineer, Pixel IP

Apple Inc

Sunnyvale, CA 9 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago High trust Above market
RTL AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification ASIC Design
3+ yrs exp
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ASIC Design Engineer

Apple Inc

Sunnyvale, CA 14 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
Verilog System Verilog RTL ASIC Design SoC Digital Signal Processing Synthesis Power-Gating AMBA AXI AHB APB Python Perl TCL Linting CDC RDC
10+ yrs exp
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ASIC Design Engineer

Apple Inc

Sunnyvale, CA 14 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday High trust Above market
Verilog System Verilog RTL ASIC SoC Digital Signal Processing AMBA AXI AHB APB Python Perl TCL Synthesis power-gating CDC RDC
5+ yrs exp
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ASIC Design Engineer

Apple Inc

Sunnyvale, CA 14 days ago $129,300–$194,700
Actively hiring Confirmed live 2 days ago Trusted Below market
Verilog System Verilog RTL ASIC Design Digital Signal Processing AMBA AXI AHB APB Synthesis Python Perl TCL SystemC C++ Finite State Machines Pipelining High-Level Synthesis
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ASIC Design Engineer, IP Integration & Implementation

Apple Inc

Sunnyvale, CA 22 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Above market
RTL ASIC Design AMBA AXI AHB APB UPF Python Perl TCL Logic Synthesis Static Timing Analysis Formal Verification Floorplanning Timing Closure Low-Power Design
3+ yrs exp
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ASIC Design Engineer, IP Integration & Implementation

Apple Inc

Sunnyvale, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
RTL ASIC Design AMBA AXI AHB APB UPF Python Perl TCL Logic Synthesis Static Timing Analysis Formal Verification Floorplanning Timing Closure Low-Power Design FPGA
10+ yrs exp
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ASIC Design Engineer, Neural Engine DMA

Apple Inc

Sunnyvale, CA 58 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago High trust Above market
Verilog SystemVerilog RTL DMA AMBA AXI AHB APB Synthesis Timing Closure Logic Equivalence Check Python Perl Tcl Formal Verification ASIC Design SoC
10+ yrs exp
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ASIC Design Engineer, Neural Engine DMA

Apple Inc

Sunnyvale, CA 58 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago High trust Competitive pay
Verilog SystemVerilog RTL DMA AMBA AXI AHB APB Synthesis Timing Closure Logic Equivalence Check Python Perl Tcl ASIC Design SoC Formal Verification Linting
3+ yrs exp
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ASIC Design Engineer, Neural Engine DMA

Apple Inc

Sunnyvale, CA 58 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday High trust Below market
Verilog SystemVerilog RTL AMBA AXI AHB APB Python Perl Tcl Synthesis Timing Closure Logic Equivalence Formal Verification SoC DMA
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ASIC Design Verification Engineer

Amazon Inc

Austin, TX +3 78 days ago $136,000–$184,000
Actively hiring Confirmed live yesterday High trust Below market
UVM SystemVerilog Verilog SystemC Matlab C DPI-C Formal Verification RTL ASIC Digital Verification Scripting CMOS
5+ yrs exp
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Lead ASIC Design Verification Engineer

Amazon Inc

Sunnyvale, CA +2 78 days ago $159,200–$215,300
Actively hiring Confirmed live yesterday High trust Above market
UVM C++ C Matlab Formal Verification System C DPI-C RTL FPGA Emulation Scripting ASIC Design Digital Verification CMOS
7+ yrs exp
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Senior ASIC Design Verification Engineer

Amazon Inc

Sunnyvale, CA +1 78 days ago $159,200–$215,300
Actively hiring Confirmed live yesterday High trust Above market
UVM C++ C System C DPI-C Formal Verification Matlab RTL FPGA Emulation Digital Verification ASIC Scripting CMOS
7+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Sunnyvale, CA 108 days ago $175,000–$280,000
Actively hiring Confirmed live 2 days ago Low trust Above market
ASIC Physical Design RTL2GDSII STA EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis Electromigration
5+ yrs exp
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ASIC Design Engineer, Pixel IP DMA

Apple Inc

Sunnyvale, CA 126 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Low trust Above market
RTL ASIC Design DMA SoC AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Power Analysis Formal Verification Machine Learning Memory Controllers Interconnects Image Processing
10+ yrs exp
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ASIC Design Engineer, Pixel IP DMA

Apple Inc

Sunnyvale, CA 126 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Low trust Above market
ASIC Design RTL DMA SoC AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Power Analysis Machine Learning Memory Controllers Interconnects Image Processing Formal Verification
3+ yrs exp
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ASIC Design Engineer, Pixel IP DMA

Apple Inc

Sunnyvale, CA 126 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Low trust Below market
ASIC RTL DMA SoC AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Power Analysis Machine Learning Memory Controllers Interconnects Image Processing Formal Verification
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Cellular ASIC Design Engineer

Apple Inc

Sunnyvale, CA 149 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
VLSI RTL to GDSII Synthesis Place and Route DFT Python TCL Perl C/C++ Unix Shell Hspice Finesim Spectre RedHawk SeaHawk Voltus SoC
10+ yrs exp
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