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Active Keyword: ASIC Design Engineer Remove filter Location: Sunnyvale Remove filter Clear all

20 of up to 20 (filtered)

ASIC Design Verification Engineer

Amazon Inc

Sunnyvale, CA +1 19 days ago $153,600–$215,000
Actively hiring Confirmed live today Trusted Above market
UVM System C C++ C Matlab Formal Verification DPI-C RTL FPGA Emulation DSP Scripting
5+ yrs exp
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ASIC Design Engineering Lead, SoC IP DMA

Apple Inc

Sunnyvale, CA 21 days ago $216,200–$394,000
Actively hiring Confirmed live today High trust Above market
ASIC Design RTL Design SoC Architecture Microarchitecture Formal Verification AMBA AXI APB Clock Gating Power Gating Timing Optimization high speed networking AI/ML Compute infrastructure, automation Power Estimation
10+ yrs exp
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ASIC Design Verification Engineer

Amazon Inc

Sunnyvale, CA +1 31 days ago $122,600–$170,000
Actively hiring Confirmed live today Trusted Below market
UVM C/C++ Formal Verification Matlab System C DPI-C RTL FPGA Emulation Scripting DSP CMOS
2+ yrs exp
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ASIC Design Engineer, Pixel IP

Apple Inc

Sunnyvale, CA 55 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
RTL Design AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification Machine Learning
10+ yrs exp
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ASIC Design Engineer, Pixel IP

Apple Inc

Sunnyvale, CA 55 days ago $150,400–$277,600
Actively hiring Confirmed live today High trust Above market
RTL Design AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification Machine Learning
3+ yrs exp
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ASIC Design Engineer

Apple Inc

Sunnyvale, CA 60 days ago $184,700–$324,800
Actively hiring Confirmed live today Low trust Above market
ASIC Design RTL Verilog System Verilog SoC Digital Design Synthesis Python Perl TCL AMBA AXI AHB APB power-gating CDC RDC Logic Equivalence Check Formal Verification
10+ yrs exp
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ASIC Design Engineer

Apple Inc

Sunnyvale, CA 60 days ago $150,400–$277,600
Actively hiring Confirmed live today Low trust Above market
Verilog System Verilog RTL ASIC Design SoC Synthesis AMBA AXI AHB APB Python Perl TCL CDC RDC Logic Equivalence Check Linting Formal Verification Digital Signal Processing power-gating
3+ yrs exp
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ASIC Design Engineer, Pixel IP

Apple Inc

Sunnyvale, CA 60 days ago $129,300–$194,700
Actively hiring Confirmed live today Low trust Below market
Verilog System Verilog RTL ASIC Design Digital Signal Processing AMBA AXI AHB APB Python Perl TCL SystemC C++ High-Level Synthesis Synthesis Power Analysis Finite State Machines
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ASIC Design Engineer, IP Integration & Implementation

Apple Inc

Sunnyvale, CA 68 days ago $150,400–$277,600
Actively hiring Confirmed live today Low trust Above market
RTL ASIC Design SoC Design AMBA AXI AHB APB UPF Python Perl TCL Logic Synthesis Static Timing Analysis Logic Equivalence Checking Formal Verification Floorplanning Timing Closure
3+ yrs exp
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ASIC Design Engineer, IP Integration & Implementation

Apple Inc

Sunnyvale, CA 90 days ago $184,700–$324,800
Actively hiring Confirmed live today Low trust Above market
ASIC Design RTL SoC Design IP Integration Logic Synthesis Static Timing Analysis Logic Equivalence Checking AMBA AXI AHB APB UPF Python Perl TCL FPGA Formal Verification Floorplanning Timing Closure
10+ yrs exp
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ASIC Design Engineer, Neural Engine DMA

Apple Inc

Sunnyvale, CA 104 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
Verilog SystemVerilog RTL ASIC Design DMA AMBA AXI AHB APB Synthesis Timing Closure Linting LEC Formal Verification Python Perl Tcl Microarchitecture SoC AI/ML Accelerators
10+ yrs exp
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ASIC Design Engineer, Neural Engine DMA

Apple Inc

Sunnyvale, CA 104 days ago $150,400–$277,600
Actively hiring Confirmed live today High trust Above market
Verilog SystemVerilog RTL ASIC Design DMA AMBA AXI AHB APB Synthesis Timing Closure Linting LEC Python Perl Tcl Formal Verification SoC AI/ML Accelerators
3+ yrs exp
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ASIC Design Verification Engineer

Amazon Inc

Austin, TX +3 124 days ago $153,600–$215,000
Actively hiring Confirmed live today Low trust Above market
SystemVerilog UVM Verilog SystemC Matlab C DPI-C Formal Verification RTL DSP CMOS Scripting
5+ yrs exp
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Senior ASIC Design Verification Engineer

Amazon Inc

Sunnyvale, CA +1 124 days ago $185,200–$250,000
Actively hiring Confirmed live today Low trust Above market
UVM C/C++ Formal Verification System C DPI-C Matlab RTL FPGA Emulation Scripting DSP CMOS
7+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA +2 154 days ago $165,000–$260,000
Actively hiring Confirmed live today Low trust Competitive pay
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Palo Alto, CA +3 154 days ago $175,000–$280,000
Actively hiring Confirmed live today Low trust Above market
ASIC Physical Design RTL2GDSII Static Timing Analysis STA FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools Floorplanning Place and Route Physical Verification Electromigration Voltage Drop
5+ yrs exp
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Senior SOC/ASIC Physical Design Engineer

SpaceX

Austin, TX +2 154 days ago
Actively hiring Confirmed live today Low trust
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route Physical Verification Electromigration Voltage Drop Logic Equivalency FinFET CMOS DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools
5+ yrs exp
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ASIC Design Engineer, Pixel IP DMA

Apple Inc

Sunnyvale, CA 171 days ago $184,700–$324,800
Actively hiring Confirmed live today Low trust Above market
ASIC Design RTL Design DMA Engines SoC AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Power Analysis Formal Verification Machine Learning Interconnects Memory Controllers Address Translation Caching
10+ yrs exp
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ASIC Design Engineer, Pixel IP DMA

Apple Inc

Sunnyvale, CA 171 days ago $150,400–$277,600
Actively hiring Confirmed live today Low trust Competitive pay
ASIC Design RTL Design DMA Engines SoC AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Power Analysis Formal Verification Machine Learning Interconnects Memory Controllers Address Translation Caching
3+ yrs exp
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ASIC Design Engineer, Pixel IP DMA

Apple Inc

Sunnyvale, CA 171 days ago $129,300–$194,700
Actively hiring Confirmed live today Low trust Below market
ASIC Design RTL Design DMA Engines SoC AMBA AXI AHB APB Synthesis Linting Logic Equivalence Check Area and Power Analysis Formal Verification Machine Learning Image Processing Interconnects Memory Controllers
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