ASIC Design Engineer, Pixel IP

Apple Inc

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$150,400–$277,600 / yr
Posted
9 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $214k
$135k most similar roles pay here $293k

This role pays more than 71% of similar roles. Most pay $168,425–$216,250 — the shaded band above. At the midpoint, this role pays about $214k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Pixel IP

As an ASIC Design Engineer - Pixel IP ANE, you will join the Hardware Technologies group to design next-generation Apple Neural Engine components. You will work within the pixel IP team to develop high-speed, high-performance subsystems while collaborating with cross-functional teams across architecture, verification, power, and physical design. Your daily responsibilities include performing RTL design, ensuring correctness in clock domain crossing designs, and partnering with formal verification and DFT teams to ensure testability. You will also work with synthesis and static timing teams to produce high-quality netlists. The role requires extensive knowledge of computer architecture, specifically bus topologies and AMBA protocols. Technical requirements include experience with synthesis, static timing analysis, and power intent. This position focuses on the technical challenges of building complex machine learning systems for AI/ML applications.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

What you'll do

  • Perform RTL design for high-speed, high-performance subsystems within the Neural Engine.
  • Collaborate with verification and formal verification teams to validate design functionality and performance.
  • Work with physical design and static timing teams to produce high-quality netlists through synthesis.
  • Analyze clock domain crossing designs to ensure technical correctness.
  • Coordinate with DFT and BIST teams to ensure the design is fully testable.
  • Implement complex computer architecture features including AMBA bus topologies and protocols.
  • Integrate power intent requirements into the hardware design process.

What we're looking for

  • Bachelor of Science degree and at least 3 years of experience.
  • Extensive knowledge of computer architecture, including bus topologies and protocols like AMBA.
  • Experience designing high-speed, high-performance compute systems.
  • Knowledge of Clock Domain Crossing (CDC) designs for correctness.
  • Experience with synthesis to produce high-quality netlists.
  • Experience with Static Timing Analysis (STA).
  • Experience working with Power Intent.

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