ASIC Design Engineer, Pixel IP

Apple Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$150,400–$277,600 / yr
Posted
55 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $190k
This role $214k
$135k $293k
below market most similar roles pay here above market

This role pays more than 70% of similar roles. Most pay $162,000–$217,525 — the blue band above. At the midpoint, this role pays about $214k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Pixel IP

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As an ASIC Design Engineer - Pixel IP ANE within the Hardware Technologies group, you will contribute to the design of the next-generation Apple Neural Engine. This role focuses on developing high-performance machine learning systems, specifically working on high-speed subsystems. Your daily responsibilities include performing RTL design, collaborating with verification and formal verification teams, and partnering with physical design and static timing teams to produce high-quality netlists through synthesis. You will also analyze clock domain crossing designs for correctness and work with DFT and BIST teams to ensure full testability. Required technical skills include extensive knowledge of computer architecture, bus topologies like AMBA, static timing analysis, and power intent. You will solve complex hardware problems to enable advanced AI and ML capabilities in future products.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

RTL Design AMBA Computer Architecture Synthesis Static Timing Analysis Clock Domain Crossing DFT BIST Power Intent Formal Verification Machine Learning

What you'll do

  • Perform RTL design on high-speed, high-performance subsystems.
  • Coordinate with verification and formal verification teams to validate design and performance.
  • Work with physical design and static timing teams to produce high-quality netlists through synthesis.
  • Analyze clock domain crossing designs to ensure functional correctness.
  • Collaborate with DFT and BIST teams to ensure the design is fully testable.
  • Implement designs utilizing bus topologies and protocols such as AMBA.

What we're looking for

  • Bachelor's degree and 3 years of experience.
  • Extensive knowledge of computer architecture, including bus topologies and protocols such as AMBA (preferred).
  • Experience working on large, high-speed compute systems (preferred).
  • Good knowledge base on Clock Domain Crossing designs (preferred).
  • Experience with Synthesis (preferred).
  • Experience with Static Timing Analysis (preferred).
  • Experience working with Power Intent (preferred).

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