ASIC Design Engineer, Neural Engine DMA

Apple Inc

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Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $150,400–$277,600 / yr
Posted: 104 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k

This role $214k

$135k $293k

below market most similar roles pay here above market

This role pays more than 66% of similar roles. Most pay $176,687–$227,300 — the blue band above. At the midpoint, this role pays about $214k versus about $202k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Neural Engine DMA

Role Posting Log in to save

JOB TITLE: ASIC Design Engineer — Neural Engine DMA As an ASIC Design Engineer on the ANE DMA Design team within the Silicon Engineering Group, you will own the design of high-performance DMA engines. You will manage the full front-end design cycle, from microarchitecture specification through tapeout, specifically focusing on moving model weights and activation tensors between the memory subsystem and the Apple Neural Engine. Your daily responsibilities include writing well-parameterized RTL, performing synthesis, timing closure, area and power analysis, linting, and logic equivalence checks. You will address complex problems like fetch sequencing, out-of-order response management, and memory system back-pressure. Required skills include Verilog or SystemVerilog, AMBA AXI, AHB, and APB protocols, and scripting in Python, Perl, or Tcl. You will also work on hardware compression, networking SoCs, and AI/ML accelerators.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

Verilog SystemVerilog RTL ASIC Design DMA AMBA AXI AHB APB Synthesis Timing Closure Linting LEC Python Perl Tcl Formal Verification SoC AI/ML Accelerators

What you'll do

Own the design of DMA subsystem blocks from microarchitecture specification through tapeout.
Write well-parameterized RTL for synthesis, timing closure, low power, and area efficiency.
Implement fetch sequencing, out-of-order response management, and memory system back-pressure logic.
Integrate address translation and resolve pipeline hazards within the DMA engine.
Perform front-end signoff tasks including synthesis, linting, and logic equivalence checks.
Write assertions and cover points to encode design intent and ensure verification completeness.
Debug failures and review test plans with design and formal verification teams.
Explore microarchitectural trade-offs to meet specific performance, power, and area targets.

What we're looking for

Bachelor's Degree plus 3 years of industry experience.
Experience designing SoC front-end RTL in Verilog or SystemVerilog through at least one tapeout (preferred).
Experience designing DMA microarchitecture including address sequencing, flow control, arbitration, or transaction ordering (preferred).
Experience with on-chip bus protocols (AMBA AXI, AHB, APB) and on-chip interconnect fabrics (preferred).
Background in hardware compression, networking SoCs, image/video processing, multimedia, or AI/ML accelerators (preferred).
Experience writing precise micro-architectural specifications (preferred).
Familiarity with scripting languages such as Python, Perl, or Tcl for design automation (preferred).

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