ASIC Design Engineer, Neural Engine DMA

Apple Inc

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$150,400–$277,600 / yr
Posted
58 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $202k
This role $214k
$135k most similar roles pay here $293k

This role pays more than 65% of similar roles. Most pay $175,000–$229,425 — the shaded band above. At the midpoint, this role pays about $214k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Neural Engine DMA

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As part of the Silicon Engineering Group, the ASIC Design Engineer — Neural Engine DMA will own the design of high-performance DMA engines that move model weights and activation tensors between memory subsystems and the Apple Neural Engine. This role involves end-to-end ownership of DMA subsystem blocks from microarchitecture specification through tapeout, addressing complex challenges like fetch sequencing, out-of-order response management, back-pressure, address translation integration, and pipeline hazard resolution. The engineer will write well-parameterized RTL for synthesis, timing closure, and power analysis while collaborating with architecture and verification teams to ensure functional correctness. Required skills include experience in Verilog or SystemVerilog, knowledge of AMBA AXI, AHB, and APB protocols, and familiarity with scripting languages like Python, Perl, or Tcl. The work focuses on the technical challenge of moving massive data volumes for on-device AI capabilities.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

Verilog SystemVerilog RTL DMA AMBA AXI AHB APB Synthesis Timing Closure Logic Equivalence Check Python Perl Tcl ASIC Design SoC Formal Verification Linting

What you'll do

  • Own the design of DMA subsystem blocks from microarchitecture specification through tapeout.
  • Write well-parameterized RTL structured for optimal synthesis, timing, and low power consumption.
  • Manage complex logic including fetch sequencing, out-of-order responses, and pipeline hazard resolution.
  • Integrate address translation and manage memory system back-pressure within the DMA engine.
  • Perform front-end signoff tasks including synthesis, timing closure, area/power analysis, and linting.
  • Develop assertions and cover points to encode design intent and ensure verification completeness.
  • Collaborate with architecture and physical implementation teams to resolve microarchitectural trade-offs.
  • Partner with verification teams to review test plans and debug functional failures.

What we're looking for

  • Bachelor's degree and at least 3 years of industry experience.
  • Experience designing SoC front-end RTL in Verilog or SystemVerilog through at least one tapeout.
  • Experience with front-end signoff tasks including synthesis, timing closure, area/power analysis, linting, and LEC.
  • Experience designing DMA microarchitecture involving address sequencing, flow control, arbitration, or transaction ordering.
  • Experience with on-chip bus protocols such as AMBA AXI, AHB, APB, and interconnect fabrics.
  • Background in adjacent domains like hardware compression, networking SoCs, multimedia, or AI/ML accelerators.
  • Ability to write precise micro-architectural specifications.
  • Familiarity with scripting languages such as Python, Perl, or Tcl for design automation.

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