ASIC Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $184,700–$324,800 / yr
Posted: 14 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k

This role $255k

$129k most similar roles pay here $346k

This role pays more than 94% of similar roles. Most pay $171,125–$223,175 — the shaded band above. At the midpoint, this role pays about $255k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer

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As an ASIC Design Engineer — Pixel IP, you will join the Hardware Technologies group to design high-performance, power-efficient system-on-chips. Working within the Pixel IP team, you will collaborate with architecture, design, and verification teams to build digital signal processing pipelines for capturing, improving, compressing, decompressing, and displaying digital still images and video. Your daily responsibilities include writing micro-architectural specifications, crafting high-quality RTL or using high-level synthesis methodologies with embedded assertions, and optimizing designs for power, timing, and area. You will utilize Verilog, SystemVerilog, and scripting languages like Python, Perl, and TCL to execute front-end tasks including linting, CDC/RDC, and logic equivalence checks. The role focuses on the technical challenge of creating pixel processing engines while navigating complex constraints involving low-power techniques such as clock- and power-gating and common on-chip bus protocols like AMBA.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

Verilog System Verilog RTL ASIC Design SoC Digital Signal Processing Synthesis Power-Gating AMBA AXI AHB APB Python Perl TCL Linting CDC RDC

What you'll do

Write high-quality RTL or use high-level synthesis methodologies with embedded assertions and cover points.
Create detailed micro-architectural specifications for pixel processing engines.
Develop digital signal processing pipelines for capturing, improving, compressing, and displaying images and video.
Optimize designs for power, timing, and area during the synthesis process.
Implement low-power design techniques such as clock-gating and power-gating.
Debug and verify functionality and performance in coordination with verification and formal verification teams.
Manage project deliverables independently to align with goals and support cross-functional engineering efforts.

What we're looking for

Bachelor's Degree in Electrical Engineering or Computer Engineering.
10+ years of relevant industry experience.
Extensive experience in SoC front-end ASIC RTL digital logic design using Verilog and SystemVerilog.
Deep experience in media, video, pixel, or display designs.
Proficiency in low-power design techniques such as clock- and power-gating.
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
Experience in front-end implementation tasks including synthesis, timing, area/power analysis, linting, CDC/RDC, and logic equivalence checks.
Knowledge of ASIC design methodology and scripting languages like Python, Perl, or TCL.

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