ASIC Design Engineer

Apple Inc

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$184,700–$324,800 / yr
Posted
60 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $255k
$129k $346k
below market most similar roles pay here above market

This role pays more than 98% of similar roles. Most pay $164,913–$218,950 — the blue band above. At the midpoint, this role pays about $255k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer

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ASIC Design Engineer — Pixel IP joins the Hardware Technologies group to design high-performance, power-efficient system-on-chips. In this front-end design role, you will work with architecture and verification teams to build pixel processing engines for capturing, improving, compressing, decompressing, and displaying digital still images and video. Your daily responsibilities include writing high-quality RTL or using high-level synthesis methodologies with embedded assertions, drafting micro-architectural specifications, and optimizing designs for power, timing, and area. You will utilize Verilog, SystemVerilog, and scripting languages like Python, Perl, and TCL. The role requires expertise in low-power techniques like clock- and power-gating, as well as familiarity with AMBA bus protocols including AXI, AHB, and APB to solve complex digital signal processing challenges.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

ASIC Design RTL Verilog System Verilog SoC Digital Design Synthesis Python Perl TCL AMBA AXI AHB APB power-gating CDC RDC Logic Equivalence Check Formal Verification

What you'll do

  • Write high-quality RTL or use high-level synthesis methodologies to design digital hardware.
  • Create detailed micro-architectural specifications for pixel processing engines.
  • Design digital signal processing pipelines for capturing, improving, and compressing images and video.
  • Synthesize designs and optimize them for power, timing, and area constraints.
  • Debug and verify functionality and performance with design and formal verification teams.
  • Implement low-power design techniques such as clock-gating and power-gating.
  • Perform front-end implementation tasks including linting, CDC/RDC, and logic equivalence checks.

What we're looking for

  • Bachelor's Degree in Electrical Engineering or Computer Engineering.
  • 10+ years of relevant industry experience.
  • Extensive experience in SoC front-end ASIC RTL digital logic design using Verilog and SystemVerilog (preferred).
  • Deep experience in media, video, pixel, or display designs (preferred).
  • Practiced in low-power design techniques such as clock- and power-gating (preferred).
  • Extensive experience working cross-functionally with architecture, design, and verification teams (preferred).
  • Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) (preferred).
  • Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, CDC/RDC, and logic equivalence checks (preferred).

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