ASIC Design Engineer, Pixel IP

Apple Inc

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$129,300–$194,700 / yr
Posted
60 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $194k
This role $162k
$117k $242k
below market most similar roles pay here above market

This role pays less than 76% of similar roles. Most pay $165,921–$223,000 — the blue band above. At the midpoint, this role pays about $162k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Pixel IP

Role Posting Log in to save

As an ASIC Design Engineer — Pixel IP within the Hardware Technologies group, you will join the Pixel IP design team to build high-performance, low-power pixel processing engines. You will work closely with architecture, design, and verification teams to create digital signal processing pipelines for capturing, improving, compressing, decompressing, and displaying digital still images and video. Your daily responsibilities include writing high-quality RTL with embedded assertions, developing micro-architectural specifications, and performing synthesis to optimize for power, timing, and area. You will utilize Verilog, SystemVerilog, and scripting languages like Python, Perl, and TCL. The role requires expertise in computer architecture fundamentals such as finite state machines, pipelining, and parallelism, along with familiarity with AMBA bus protocols and digital signal processing concepts.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

Verilog System Verilog RTL ASIC Design Digital Signal Processing AMBA AXI AHB APB Python Perl TCL SystemC C++ High-Level Synthesis Synthesis Power Analysis Finite State Machines

What you'll do

  • Write high-quality RTL with embedded assertions and cover points for digital hardware design.
  • Author detailed micro-architectural specifications for pixel processing engines.
  • Create digital signal processing pipelines for capturing, improving, and compressing images and video.
  • Synthesize designs and optimize for power, timing, and area constraints.
  • Debug and verify functionality and performance with design and formal verification teams.
  • Explore hardware solutions that maximize performance while minimizing power and area.

What we're looking for

  • Bachelor's Degree in Electrical Engineering or Computer Engineering.
  • Knowledge of front-end ASIC RTL digital logic design using Verilog or SystemVerilog (preferred).
  • Strong problem-solving skills using finite state machines, pipelining, parallelism, and computer-architecture fundamentals (preferred).
  • Good collaboration skills with excellent written and verbal communication skills (preferred).
  • Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) (preferred).
  • Knowledge of front-end implementation tasks such as synthesis and timing/area/power analysis (preferred).
  • Familiarity with relevant scripting languages such as Python, Perl, or TCL (preferred).
  • Familiarity with High-Level Synthesis, SystemC/C++, or digital signal processing concepts (preferred).

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