ASIC Design Engineer

Apple Inc

Confirmed live 2 days ago Trusted

Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$129,300–$194,700 / yr
Posted
14 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $198k
This role $162k
$117k most similar roles pay here $242k

This role pays less than 77% of similar roles. Most pay $172,000–$224,175 — the shaded band above. At the midpoint, this role pays about $162k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer

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As an ASIC Design Engineer — Pixel IP, you will join the Hardware Technologies group to develop high-performance, power-efficient system-on-chip processing engines. Working within the Pixel IP design team, you will collaborate with architecture, design, and verification teams to build digital signal processing pipelines for capturing, improving, compressing, decompressing, and displaying digital still images and video. Your daily responsibilities include writing high-quality RTL with embedded assertions, creating detailed micro-architectural specifications, and performing synthesis to optimize for power, timing, and area. You will utilize Verilog or SystemVerilog, and potentially Python, Perl, TCL, or SystemC/C++. The role requires expertise in computer architecture fundamentals like finite state machines, pipelining, and parallelism, alongside familiarity with AMBA bus protocols such as AXI, AHB, and APB to solve complex challenges in image and video processing.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

Verilog System Verilog RTL ASIC Design Digital Signal Processing AMBA AXI AHB APB Synthesis Python Perl TCL SystemC C++ Finite State Machines Pipelining High-Level Synthesis

What you'll do

  • Write high-quality RTL with embedded assertions and cover points for digital hardware design.
  • Create detailed micro-architectural specifications for pixel processing engines.
  • Develop digital signal processing pipelines for capturing, improving, compressing, and displaying images and video.
  • Optimize designs for power, timing, and area during the synthesis process.
  • Collaborate with cross-functional teams to balance performance, power, and area constraints.
  • Debug and verify functionality and performance in coordination with verification and formal verification teams.

What we're looking for

  • Bachelor's Degree in Electrical Engineering or Computer Engineering.
  • Knowledge of front-end ASIC RTL digital logic design using Verilog or SystemVerilog.
  • Proficiency in computer architecture fundamentals including finite state machines, pipelining, and parallelism.
  • Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
  • Knowledge of front-end implementation tasks including synthesis and timing, area, and power analysis.
  • Familiarity with scripting languages such as Python, Perl, or TCL.
  • Experience with High-Level Synthesis and hardware design using SystemC/C++ is a plus.
  • Background in digital signal processing concepts is a plus.

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