below marketmost similar roles pay hereabove market
This role pays more than
69%
of similar roles. Most pay
$164,913–$223,000
— the blue band above.
At the midpoint, this role pays about
$214k
versus about
$194k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
ASIC Design Engineer — Pixel IP joins the Hardware Technologies group to design high-performance, power-efficient system-on-chips. In this front-end design role, you will work with architecture and verification teams to build pixel processing engines for capturing, improving, compressing, decompressing, and displaying digital still images and video. Your daily responsibilities include writing high-quality RTL or using high-level synthesis methodologies with embedded assertions, drafting detailed micro-architectural specifications, and optimizing designs for power, timing, and area. You will utilize Verilog, SystemVerilog, and scripting languages like Python, Perl, and TCL. The role requires expertise in digital signal processing pipelines, low-power techniques like clock-gating, and on-chip bus protocols such as AMBA. You will solve complex hardware challenges to enable seamless image and video processing for consumer devices.
What does a ASIC Design Engineer earn in California?
Median $214000 from 49 postings across 7 companies.
Write high-quality RTL or use high-level synthesis methodologies to design digital hardware.
Create detailed micro-architectural specifications for pixel processing engines.
Design digital signal processing pipelines for capturing, improving, and compressing images and video.
Synthesize designs and optimize them for power, timing, and area.
Embed assertions and cover points into the RTL design.
Debug and verify functionality and performance with design and formal verification teams.
Perform front-end implementation tasks including linting, CDC/RDC, and logic equivalence checks.
What we're looking for
Bachelor's Degree in Electrical Engineering or Computer Engineering.
3+ years of relevant industry experience.
Experience in SoC front-end ASIC RTL digital logic design using Verilog or SystemVerilog (preferred).
Previous experience in media, video, pixel, or display designs (preferred).
Experience working cross-functionally with architecture, design, and verification teams to specify, design, and debug designs (preferred).
Good collaboration skills with strong written and verbal communication skills (preferred).
Familiarity with low-power design techniques such as clock- and power-gating (preferred).
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) (preferred).
Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, CDC/RDC, and logic equivalence checks (preferred).
Industry exposure to ASIC/FPGA design methodology and scripting languages like Python, Perl, or TCL (preferred).
Verilog
System Verilog
RTL
ASIC Design
Digital Signal Processing
AMBA
AXI
AHB
APB
Python
Perl
TCL
SystemC
C++
High-Level Synthesis
Synthesis
Power Analysis
Finite State Machines