ASIC Design Engineer, IP Integration & Implementation

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$150,400–$277,600 / yr
Posted
22 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $189k
This role $214k
$133k most similar roles pay here $293k

This role pays more than 71% of similar roles. Most pay $162,000–$216,250 — the shaded band above. At the midpoint, this role pays about $214k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, IP Integration & Implementation

As part of the Hardware Technologies group, the ASIC Design Engineer — IP Integration & Implementation joins the Pixel IP design team to develop high-performance, power-efficient system-on-chip processing engines for capturing and displaying images and video. This front-end role involves writing micro-architectural and integration specifications, crafting high-quality RTL with embedded assertions, and collaborating with physical design teams to optimize timing, area, and power in silicon. The engineer ensures designs adhere to industry standards for power, clock, and reset domains while working with verification teams to debug functionality. Key technical requirements include experience with ASIC/FPGA design methodologies like logic synthesis, static timing analysis, and floorplanning. Candidates should be familiar with AMBA bus protocols (AXI, AHB, APB), UPF power intent specifications, and scripting languages such as Python, Perl, or TCL to solve complex multimedia integration challenges.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

What you'll do

  • Write detailed micro-architectural and integration specifications for multimedia IP.
  • Design digital hardware by writing high-quality RTL with embedded assertions and cover points.
  • Optimize timing, area, and power in collaboration with physical design teams.
  • Implement designs that follow industry best practices for power, clock, and reset domains.
  • Debug and verify functionality and performance alongside verification and formal verification teams.
  • Integrate complex subsystems into high-performance, low-power pixel processing engines.

What we're looking for

  • Bachelor's degree and 3+ years of relevant industry experience.
  • Experience in IP/SoC design, integration at the chip or subsystem level, and implementation (preferred).
  • Knowledge of ASIC/FPGA design methodology including logic synthesis, static timing analysis, and logic equivalence checking (preferred).
  • Experience with system design methodologies involving multiple clock and reset domains (preferred).
  • Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) (preferred).
  • Experience in low-power design, tools, and methodologies including UPF power intent specification (preferred).
  • Familiarity with scripting languages like Python, Perl, or TCL (preferred).
  • Strong collaboration skills with excellent written and verbal communication (preferred).

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