ASIC Design Engineering Lead, SoC IP DMA

Apple Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$216,200–$394,000 / yr
Posted
21 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k
This role $305k
$126k $423k
below market most similar roles pay here above market

This role pays more than 99% of similar roles. Most pay $177,250–$229,100 — the blue band above. At the midpoint, this role pays about $305k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineering Lead, SoC IP DMA

Role Posting Log in to save

The ASIC Design Engineering Lead - SoC IP DMA will lead a team within the SoC IP DMA design effort, balancing people management with hands-on technical contribution. The role involves guiding the team through the full front-end design cycle, including microarchitecture, RTL delivery, and debug. Key responsibilities include defining micro-architecture, providing technical guidance, reviewing team work, and driving the development of design infrastructure and automation using AI tools. The candidate must perform effort, area, and power estimates while managing project schedules. Required skills include expertise in SoC architecture for high-speed networking, AI/ML compute, and memory subsystems. Technical competencies include arbitration, flow control, address translation, caching, pipelining, and AMBA protocols like AXI and APB, alongside low-power design techniques and timing optimization.

Skills

ASIC Design RTL Design SoC Architecture Microarchitecture Formal Verification AMBA AXI APB Clock Gating Power Gating Timing Optimization high speed networking AI/ML Compute infrastructure, automation Power Estimation

What you'll do

  • Lead the team through the full front-end design cycle including microarchitecture, RTL delivery, and debug.
  • Define and document micro-architectures while providing high-level technical guidance and design reviews.
  • Perform hands-on RTL design, verification strategy, and infrastructure development tasks.
  • Scope features and generate effort, area, power estimates, and bottoms-up project schedules.
  • Drive the development of design infrastructure, automation, and the strategic use of AI tools.
  • Manage and mentor a team of engineers to foster technical and professional growth.
  • Track execution, surface risks early, and communicate project status to management and stakeholders.
  • Partner with cross-functional teams to align on plans, milestones, and deliverables.

What we're looking for

  • BS degree in a relevant field.
  • Minimum of 20 years of relevant industry experience.
  • 10+ years of hands-on experience in front-end ASIC design (preferred).
  • Experience in technical leadership, including setting technical direction and managing multi-person deliverables (preferred).
  • Experience managing people on a team (preferred).
  • Outstanding written and verbal communication skills and cross-functional collaboration instincts (preferred).
  • Excellent project planning skills including bottom-up scheduling, effort, area, and power estimation (preferred).
  • Solid understanding of SoC architecture, high-performance designs, and AMBA protocols (preferred).

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