ASIC Design Engineer, Neural Engine DMA

What you'll do

• Design high-performance DMA engines to move model weights and activation tensors between memory and the Neural Engine.
• Own the full design cycle from microarchitecture specification through RTL implementation and tapeout.
• Write well-parameterized RTL in Verilog or SystemVerilog optimized for timing, power, and area.
• Develop complex logic for address sequencing, flow control, arbitration, and transaction ordering.
• Create detailed micro-architectural specifications to serve as the authoritative reference for design and verification teams.
• Perform front-end signoff tasks including synthesis, timing closure, linting, and logic equivalence checks.
• Collaborate with architecture and physical implementation teams to resolve trade-offs regarding performance and power targets.
• Partner with verification teams to review test plans, debug failures, and ensure functional correctness.

What we're looking for

• Bachelor's degree and 10 years of industry experience.
• Experience designing SoC front-end RTL in Verilog or SystemVerilog through multiple tapeouts.
• Experience with front-end signoff including synthesis, timing closure, area/power analysis, linting, and LEC.
• Experience designing DMA microarchitecture involving address sequencing, flow control, arbitration, or transaction ordering.
• Experience with on-chip bus protocols (AMBA AXI, AHB, APB) and interconnect fabrics.
• Background in high-bandwidth domains such as networking SoCs, multimedia IP, or AI/ML accelerators.
• Ability to write precise micro-architectural specifications for design, verification, and integration teams.
• Familiarity with scripting languages like Python, Perl, or Tcl for design automation.