ASIC Design Engineer, Neural Engine DMA

Apple Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$184,700–$324,800 / yr
Posted
104 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $255k
$129k $346k
below market most similar roles pay here above market

This role pays more than 97% of similar roles. Most pay $176,687–$227,300 — the blue band above. At the midpoint, this role pays about $255k versus about $202k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Neural Engine DMA

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ASIC Design Engineer — Neural Engine DMA As part of the Silicon Engineering Group, the ASIC Design Engineer — Neural Engine DMA will design high-performance DMA engines to move model weights and activation tensors between memory and the Apple Neural Engine. This role involves end-to-end ownership of DMA subsystem blocks, from microarchitecture specification through tapeout. Key responsibilities include writing well-parameterized RTL, performing front-end signoff tasks like synthesis and timing closure, and collaborating with verification and physical implementation teams. The engineer must address complex problems such as decomposing tensor surfaces into fetch sequences, maximizing throughput, and maintaining data consistency. Required skills include Verilog or SystemVerilog, AMBA AXI, AHB, and APB protocols, and scripting in Python, Perl, or Tcl. The work focuses on on-device AI capabilities like computational photography and live language translation.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

Verilog SystemVerilog RTL ASIC Design DMA AMBA AXI AHB APB Synthesis Timing Closure Linting LEC Formal Verification Python Perl Tcl Microarchitecture SoC AI/ML Accelerators

What you'll do

  • Own DMA subsystem blocks from microarchitecture specification through RTL implementation and tapeout.
  • Write well-parameterized RTL for clean timing and low power including assertions and cover points.
  • Perform front-end signoff tasks including synthesis, timing closure, area and power analysis, linting, and LEC.
  • Decompose tensor surfaces into efficient fetch sequences to maximize throughput under memory system conditions.
  • Manage multi-level arbitration, transaction ordering, and data consistency across concurrent streams.
  • Size latency-tolerant buffering structures and ensure security and state isolation.
  • Review test plans and debug failures with design and formal verification teams to ensure functional correctness.

What we're looking for

  • 10 years of industry experience.
  • Experience designing SoC front-end RTL in Verilog or SystemVerilog through multiple tapeouts (preferred).
  • Experience collaborating across design verification, formal verification, architecture, and physical implementation teams (preferred).
  • Experience designing DMA microarchitecture including address sequencing, flow control, arbitration, or transaction ordering (preferred).
  • Experience with on-chip bus protocols (AMBA AXI, AHB, APB) and on-chip interconnect fabrics (preferred).
  • Background in networking SoCs, image/video processing pipelines, multimedia IP, or AI/ML accelerators (preferred).
  • Familiarity with scripting languages such as Python, Perl, or Tcl (preferred).
  • Bachelors Degree.

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