Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: Senior ASIC Design Engineer Remove filter Location: Santa Clara Remove filter Clear all

13 of up to 20 (filtered)

Senior ASIC Design Engineer, DFX

Nvidia

Santa Clara, CA 7 days ago $168,000–$264,500
Actively hiring Confirmed live 2 days ago Posted this week High trust Above market
DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Power Optimization Fuse Controller Verification Synthesis
8+ yrs exp
Save

Senior ASIC Design Engineer, Clocks IP

Nvidia

Santa Clara, CA +1 9 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting
3+ yrs exp Hybrid
Save

Senior ASIC Design Engineer

Nvidia

Remote (Santa Clara, CA) 9 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Design RTL Design SoC Integration Logic Synthesis Timing Analysis Python Perl C++ UCIe Digital Design Verification Methodology Memory Controllers DMA Boot Controllers Fuse Controllers
5+ yrs exp Remote Hybrid
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 28 days ago $168,000–$264,500
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis VLSI Computer Architecture C++ Python Perl Bus Protocols Interconnect Networks DMA Engines Digital Systems
8+ yrs exp Hybrid
Save

Senior ASIC Design Verification Infrastructure and Tools Engineer

Nvidia

Remote (Santa Clara, CA) +3 29 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics
5+ yrs exp Remote
Save

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 32 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
Physical Design Synthesis Timing Analysis Floor-planning Verilog ASIC Design Flow RTL Design Verification DFT ECO High-frequency Design Micro-architecture
5+ yrs exp
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 32 days ago $168,000–$264,500
Actively hiring Confirmed live yesterday Trusted Above market
Verilog System-Verilog ASIC Design RTL Logic Synthesis Timing Analysis Computer Architecture GPU Memory Systems Interconnect Networks ECO AI Workflows Autonomous Agents
8+ yrs exp
Save

Senior ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 37 days ago $136,000–$218,500
Actively hiring Confirmed live 2 days ago High trust Competitive pay
ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture
5+ yrs exp Hybrid
Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 46 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Trusted Competitive pay
ASIC Design Verilog System-Verilog RTL VLSI Digital Design Synthesis Timing Analysis CDC Formal Equivalence Python Perl Tcl Make files DFT mixed signal Post-Si Bringup Agentic AI
3+ yrs exp Hybrid
Save

Senior ASIC Design Verification Engineer

Nvidia

Santa Clara, CA 46 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Trusted Competitive pay
System Verilog UVM SVA Verilog VCS Questa Perl Tcl Make files Gate Level Simulation Formal Equivalence LLMs Agentic AI Frameworks Mixed Signal Design Functional Coverage Co-simulation
5+ yrs exp Hybrid
Save

Senior ASIC Design Engineer, Agentic AI

Nvidia

Santa Clara, CA +2 77 days ago $168,000–$264,500
Actively hiring Confirmed live 2 days ago High trust Above market
ASIC Design RTL Verilog Micro-architecture Logic Synthesis Timing Analysis VLSI Python LLM Agentic AI RAG Vector Databases Machine Learning Computer Architecture Digital Systems Data Structures Algorithms
8+ yrs exp
Save

Senior ASIC Floorplan Design Engineer

Nvidia

Santa Clara, CA +1 82 days ago $196,000–$310,500
Actively hiring Confirmed live 2 days ago High trust Above market
ASIC Floorplan Physical Design SOC CPU GPU DFT Place and Route Timing Closure Python C++ Perl Agentic AI Algorithm Development Chiplet Power/Clock/Reset Distribution
10+ yrs exp
Save

Senior ASIC Floorplan Design Engineer

Nvidia

Santa Clara, CA +1 113 days ago $196,000–$310,500
Actively hiring Confirmed live 2 days ago Trusted Above market
ASIC Floorplan VLSI Computer Architecture Verilog System Verilog Python Perl C/C++ CAD Physical Design Timing Closure Clock Distribution Packaging
10+ yrs exp
Save