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DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Place & Route Power Optimization Fuse Controller DFT IP Verification Synthesis +12 more Show less

ASIC Design RTL Design Logic Synthesis Timing Analysis SoC Integration Python Perl C++ UCIe Digital Design Verification Methodology Boot Controllers Reset Controllers Memory Controllers DMA +10 more Show less

RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis C++ Python Perl VLSI Design Computer Architecture DMA Engines Bus Protocols Interconnect Networks Digital Systems Computer Arithmetic +11 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation +8 more Show less

ASIC Design RTL Design Verilog System Verilog Python Perl Logic Synthesis Timing Analysis VLSI Computer Architecture VCS Verdi GDB Functional Coverage Assertion-Based Verification Embedded Processors SoC GPU +13 more Show less

Physical Design Python C++ Perl DFT Place and Route Timing Closure Power/Clock/Reset Distribution Agentic AI Chiplet Packaging Algorithm Development +7 more Show less

ASIC Design RTL Design Verilog VHDL Synthesis Timing Analysis CHI CXL PCI-E PERL CAD Tools Hardware-managed Coherency System Level Caches Protocol Bridges Asynchronous Interfaces +10 more Show less

RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV SOC Verification +6 more Show less

ASIC Design RTL Verilog Micro-architecture VLSI Logic Synthesis Timing Analysis DFT Computer Architecture PCI-Express CXL Python Perl C/C++ CMOS Post-silicon Validation Floor-planning ECO Bus Protocols Interconnect Networks +15 more Show less

SystemVerilog UVM ASIC Verification Python C/C++ Perl VCS Verdi DFT UPF Machine Learning SoC Functional Coverage Assertion-based Verification GDS +10 more Show less

ASIC Design RTL Design Verilog System Verilog Python C/C++ Perl Logic Synthesis Timing Analysis VCS Debussy GDB Formal Verification Assertion-Based Verification Computer Architecture VLSI Simulation Functional Coverage +13 more Show less

ASIC SystemVerilog Verilog UVM Python Perl VCS Verdi Xcelium RTL Pre-silicon Verification infrastructure, automation Simulation Debug Root-cause Analysis +10 more Show less

Physical Design ASIC Design Flow Synthesis Timing Analysis Verilog RTL Design DFT ECO Floor-planning High-Frequency Design Micro-architecture +6 more Show less

ASIC Design Verilog System-Verilog RTL Logic Synthesis Timing Analysis Computer Architecture GPU ECO Micro-architecture Interconnect Networks Caches Coherency AI Workflows Tapeout Debugging +11 more Show less

ASIC Design Verilog System-Verilog RTL Design VLSI Digital Systems Design Computer Architecture Synthesis Timing Analysis CDC Formal Equivalence Python Perl Tcl Make files DFT Mixed Signal Design Post-Si Bringup Agentic AI flows +14 more Show less

System Verilog UVM Verilog SVA VCS Questa Perl Tcl Make Formal Equivalence Gate Level Simulation LLMs Agentic AI Functional Coverage Mixed Signal Design Co-simulation ASIC Design Verification +12 more Show less

ASIC Design RTL Design Verilog Micro-architecture Logic Synthesis Timing Analysis Python LLM RAG Vector Databases Machine Learning VLSI Design Computer Architecture Agentic AI Digital Systems +10 more Show less

ASIC Floorplan Design VLSI Computer Architecture Verilog System Verilog Python Perl C/C++ CAD Physical Design P&R Timing Closure Power/Clock Distribution Packaging +9 more Show less