Senior ASIC Design Engineer

Nvidia

Confirmed live today Low trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Employment: Full-time
Posted: 92 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $192k

$136k $232k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $167,737–$216,250.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer

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The Senior ASIC Design Engineer joins the Circuit Solutions Group to drive micro-architecture and digital design implementation for innovative hardware security, clocking, voltage regulation, and silicon correlation IPs. This role involves developing scalable RTL designs, executing synthesis, and performing timing analysis using advanced CAD tools and process technologies. Key responsibilities include functional verification, CDC checks, formal equivalence, and supporting post-si bringup and debug activities. Candidates must possess experience in logic design, Verilog, and SystemVerilog, with a deep understanding of physical design, VLSI, and computer architecture. Required skills include programming in Perl or Python and managing multiple clock domains. The work addresses technical challenges across consumer graphics, self-driving cars, and artificial intelligence, requiring expertise in mixed-signal concepts and custom designed IP solutions.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

ASIC Design Verilog System-Verilog RTL Design VLSI Digital Systems Design Computer Architecture Synthesis Timing Analysis CDC Formal Equivalence Python Perl Tcl Make files DFT Mixed Signal Design Post-Si Bringup Agentic AI flows

What you'll do

Implement micro-architecture and digital designs for hardware security, clocking, voltage regulation, and silicon correlation.
Develop scalable RTL designs using innovative CAD tools and the latest process technologies.
Execute synthesis and perform detailed timing analysis for hardware designs.
Perform functional verification, CDC checks, and formal equivalence.
Support post-silicon bringup and debug activities.
Develop and craft design tools and flows, including Agentic AI flows.

What we're looking for

BS in Electrical Engineering, Computer Engineering, or a related degree is required; advanced degrees are a plus (preferred).
3+ years of relevant proven experience in logic design, Verilog and/or System-Verilog with a deep understanding of physical design and VLSI.
Experience with multiple clock domains and asynchronous interfaces.
Exposure to Digital Systems design and computer architecture.
Programming skills in PERL or Python.
Excellent communication and interpersonal skills.
Experience with all stages of ASIC design flow including front end design, verification, DFT, timing analysis, ECO, ATE test development, and post-si bringup (preferred).
Proficiency in scripting languages such as Perl, Tcl, Make files, and automation methods (preferred).

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