Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type: On-site
Location: Santa Clara, CAHillsboro, OR
Salary: $136,000–$218,500 / yr
Posted: 32 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k

This role $177k

$124k most similar roles pay here $244k

This role pays less than 61% of similar roles. Most pay $176,687–$224,362 — the shaded band above. At the midpoint, this role pays about $177k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Role Posting Log in to save

As a Senior ASIC Physical Design Engineer, Cache Coherent Interconnects, you will join the CPU Cache Coherent Interconnects Design Team to manage the physical design of on-chip interconnect networks and last-level caches. Your daily responsibilities include performing synthesis, achieving timing, area, performance, and power goals, and evaluating physical designs for next-generation coherent interconnects and system-level caches while collaborating with logic designers on micro-architecture definition. The role requires expertise in high-frequency design, floor-planning, and industry standard physical design tools. You should possess a deep understanding of ASIC design flow, including RTL design, verification, DFT, and ECO. Preferred skills include Verilog proficiency and experience in processor or high-performance semiconductor designs. This role focuses on the technical challenge of developing high-performance interconnects and cache systems for advanced computing architectures.

Skills

Physical Design Synthesis Timing Analysis Floor-planning Verilog ASIC Design Flow RTL Design Verification DFT ECO High-frequency Design Micro-architecture

What you'll do

Perform physical design for CPU on-chip interconnect networks and last-level caches.
Execute synthesis to achieve specific timing, area, performance, and power goals.
Achieve timing closure for high-frequency semiconductor designs.
Evaluate physical design for next-generation coherent interconnects and system-level caches.
Perform floor-planning and timing analysis using industry standard physical design tools.
Collaborate with the logic design team on micro-architecture definition and feasibility.

What we're looking for

Master’s Degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent experience.
5+ years of experience in processor or other related high-performance semiconductor designs.
Expertise in physical design for high-frequency systems including synthesis, timing analysis, and floor-planning.
In-depth knowledge of industry standard physical design tools is required.
Experience in interconnect, cache, or core design (preferred).
Verilog expertise (preferred).
Deep understanding of ASIC design flow including RTL design, verification, DFT, and ECO (preferred).
Strong communication and interpersonal skills are required to work in a dynamic, global team.

Save