Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAHillsboro, OR
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
78 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $177k
$123k $258k
below market most similar roles pay here above market

This role pays less than 66% of similar roles. Most pay $177,250–$224,075 — the blue band above. At the midpoint, this role pays about $177k versus about $201k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Role Posting Log in to save

As a Senior ASIC Physical Design Engineer, Cache Coherent Interconnects, you will join the CPU Cache Coherent Interconnects Design Team to manage the physical design of the CPU on-chip interconnect network and last-level caches. Your primary responsibilities include performing synthesis and achieving specific timing, area, performance, and power goals for next-generation coherent interconnects and system-level caches. You will collaborate with the logic design team on micro-architecture definition and feasibility. The role requires expertise in high-frequency design, floor-planning, and timing analysis using industry standard physical design tools. Required skills include a Master’s Degree in Electrical Engineering, Computer Engineering, or Computer Science, along with experience in ASIC design flow, RTL design, verification, DFT, and ECO. Verilog expertise is preferred for this high-performance semiconductor design work.

Skills

Physical Design ASIC Design Flow Synthesis Timing Analysis Verilog RTL Design DFT ECO Floor-planning High-Frequency Design Micro-architecture

What you'll do

  • Perform physical design for CPU on-chip interconnect networks and last-level caches.
  • Execute synthesis to achieve timing, area, performance, and power goals.
  • Evaluate physical design for next-generation coherent interconnects and system-level caches.
  • Collaborate with logic design teams on micro-architecture definition and feasibility.
  • Conduct timing analysis and floor-planning for high-frequency designs.
  • Manage ECOs and utilize industry-standard physical design tools.
  • Support the full ASIC design flow including RTL design and verification.

What we're looking for

  • Master’s Degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent experience.
  • 5+ years of experience in processor or other related high-performance semiconductor designs.
  • Physical design expertise in high-frequency design, including hands-on synthesis, timing analysis, and floor-planning.
  • In-depth knowledge of industry standard physical design tools.
  • Experience in interconnect, cache, or core design (preferred).
  • Verilog expertise (preferred).
  • Deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO (preferred).
  • Strong communication and interpersonal skills with the ability to work in a dynamic, global team.

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