Senior ASIC Design Engineer, Clocks IP

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CAAustin, TX
Salary
$136,000–$218,500 / yr
Posted
9 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $177k
$126k most similar roles pay here $229k

This role pays less than 53% of similar roles. Most pay $169,500–$215,537 — the shaded band above. At the midpoint, this role pays about $177k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer, Clocks IP

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Senior ASIC Design Engineer – Clocks IP will join the clocks group to architect clock domains for GPU and CPU designs while satisfying functional, physical, and testing requirements. The role involves collaborating with front-end, floor-planning, back-end, software, and silicon solution teams to manage architectural constraints, improve Power, Performance, and Area (PPA), and implement new clocking topologies in RTL. You will participate in the end-to-end ASIC execution cycle, including micro-architecture, design implementation, sign-off checks, and silicon bringup. Required skills include experience in Verilog RTL design, logic synthesis, and verification, alongside proficiency in Python or other scripting languages. Candidates should possess a deep understanding of logic optimization, PPA trade-offs, and sub-micron silicon issues like noise and cross-talk. The work focuses on solving complex clocking challenges for high-speed GPU and CPU architectures within the semiconductor space.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting

What you'll do

  • Architect clock domains to satisfy functional, physical, and testing design requirements for GPU and CPU chips.
  • Implement new clocking topologies in RTL while optimizing for Power, Performance, and Area (PPA).
  • Evaluate trade-offs across DFx, physical implementation, and power optimization to ensure timing closure.
  • Develop solutions with the physical design and timing teams to support high-speed clocking.
  • Deliver clock RTL information to GPU, CPU, SOC verification, timing, and DFT teams.
  • Participate in the end-to-end ASIC execution cycle from micro-architecture and implementation to silicon bringup.
  • Triage silicon and programming bugs in the lab in coordination with the silicon solution team.

What we're looking for

  • BS in Electrical Engineering or equivalent experience (MS preferred).
  • 3+ years of relevant work experience.
  • Experience in RTL design using Verilog, verification, and logic synthesis.
  • Strong coding skills in Python or other industry-standard scripting languages.
  • Deep understanding of logic optimization techniques and PPA trade-offs.
  • Ability to collaborate with multiple teams and excellent interpersonal skills.
  • Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.
  • Experience in implementing on-chip clocking networks or hands-on silicon debug is a bonus.

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