Senior ASIC Design Engineer, Clocks IP

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CAAustin, TX
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
21 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $190k
This role $177k
$126k $233k
below market most similar roles pay here above market

This role pays less than 57% of similar roles. Most pay $164,250–$216,250 — the blue band above. At the midpoint, this role pays about $177k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1626 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1115 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer, Clocks IP

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The Senior ASIC Design Engineer – Clocks IP will join the clocks group to architect clock domains for GPU and CPU components. This role involves designing clocking topologies in RTL to satisfy functional, physical, and testing requirements while optimizing for Power, Performance, and Area. The engineer will collaborate with front design, floor-planning, back end, software, and silicon solution teams to manage clock programming sequences, physical floorplans, and silicon bug triaging. Key responsibilities include delivering clock RTL information to verification and DFT teams and participating in the end-to-end ASIC execution cycle from micro-architecture to silicon bringup. Required skills include Verilog for RTL design, logic synthesis, and Python or other scripting languages. Candidates must understand logic optimization, PPA trade-offs, and sub-micron silicon issues like noise and cross-talk.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV SOC Verification

What you'll do

  • Architect the clock domain to satisfy functional, physical, and testing design requirements.
  • Design GPU and CPU clocks to meet architectural, design, and physical constraints.
  • Improve PPA by evaluating trade-offs across DFx, physical implementation, and power optimization.
  • Implement new clocking topologies in RTL.
  • Develop solutions for supporting high-speed clocking with the physical design and timing teams.
  • Deliver clock RTL information to GPU, CPU, SOC verification, timing, and DFT teams.
  • Participate in the end-to-end ASIC cycle from micro-architecture to silicon bringup.
  • Triage silicon and programming bugs in the lab with the silicon solution team.

What we're looking for

  • BS in Electrical Engineering or equivalent experience.
  • MS in Electrical Engineering (preferred).
  • 3+ years of relevant work experience.
  • Deep understanding of logic optimization techniques and PPA trade-offs.
  • Experience in RTL design (Verilog), verification, and logic synthesis.
  • Strong coding skills in Python or other industry-standard scripting languages.
  • Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects (preferred).
  • Experience with clocks controller, clocks logic design, and scalable designs (preferred).

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