Senior ASIC Design Engineer, Agentic AI

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TXDurham, NC
Salary
$168,000–$264,500 / yr
Posted
77 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $216k
$137k most similar roles pay here $278k

This role pays more than 74% of similar roles. Most pay $172,000–$219,043 — the shaded band above. At the midpoint, this role pays about $216k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Design Engineer, Agentic AI

Role Posting Log in to save

Senior ASIC Design Engineer - Agentic AI will join the GPU Design Methodology team as part of the AI for Chip Design group to develop agentic AI solutions that craft micro-architecture and implement RTL. The role involves documenting design guidelines to ensure high performance, area, and power efficiency while delivering verified, synthesis and timing clean designs. You will build LLM-powered engineering assistants and multi-turn, multi-modal dialogue systems to solve complex chip design problems. Required expertise includes Verilog for RTL development, Python for rapid prototyping, and deep knowledge of data structures and algorithms. Candidates must possess experience in fine-tuning large language models, building RAG pipelines, and managing vector databases. The work focuses on the intersection of research and engineering to automate and innovate within the domain of ASIC design flow, including logic synthesis and timing analysis.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

ASIC Design RTL Verilog Micro-architecture Logic Synthesis Timing Analysis VLSI Python LLM Agentic AI RAG Vector Databases Machine Learning Computer Architecture Digital Systems Data Structures Algorithms

What you'll do

  • Document and deliver design guidelines to help the ASIC team implement high performance, area, and power efficient RTL.
  • Develop agentic AI solutions to craft micro-architecture and implement RTL for chip designs.
  • Deliver fully verified, synthesis and timing clean designs for SoCs and GPUs.
  • Design and deploy LLM-powered solutions for engineering assistants and multi-turn dialogue systems.
  • Build advanced multi-agent systems, RAG pipelines, and vector databases to solve complex design problems.
  • Integrate machine learning advancements into chip design tools and workflows.
  • Coordinate with tool owners and designers to ensure agentic solutions meet technical requirements.

What we're looking for

  • Master's or PhD degree in Electrical Engineering, Computer Science/Engineering, or a related field (or equivalent experience).
  • 8+ years of meaningful work experience.
  • Experience in micro-architecture and RTL development using Verilog for complex designs.
  • Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.
  • Exposure to Digital systems, VLSI design, Computer Architecture, and Computer Arithmetic.
  • Proficiency in rapid prototyping using Python with strong knowledge of data structures, algorithms, and software engineering principles.
  • Experience with fine-tuning large language models, building multi-agent systems, RAG pipelines, and vector databases.
  • Strong analytical, communication, and interpersonal skills to thrive in distributed teams.

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