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Python SystemVerilog UVM VCS Verdi Jenkins Make CI/CD Perl Docker Kubernetes Terraform AWS GCP Git GitHub Mercurial SVN Prometheus Grafana AI Machine_Learning +17 more Show less

Verilog SysVerilog C++ Python Perl TCL AgenticAI ClaudeCode Cursor CoPilot EDA ASIC Design for Testing Scan ATPG JTAG +11 more Show less

Verilog Python RTL Logic Synthesis CI/CD Sub-micron Silicon Issues Clocking Networks Clocks Controller Power Optimization Noise Analysis Cross-talk OCV Effects Scalable Designs Silicon Debug +9 more Show less

Verilog SystemVerilog Python Perl C++ CAD VLSI ComputerArchitecture ChipFloorplan PowerClockDistribution Packaging P&R TimingClosure +8 more Show less

Python Perl Verilog SystemVerilog dc_shell VCS Debussy GDB Kubernetes Terraform CI/CD Git Unix/Linux +8 more Show less

Verilog System-Verilog RTL ASIC Logic Design Computer Architecture Digital Systems Timing Analysis ECO Post Silicon Debug Arbiters Scheduling Synchronization Bus Protocols Interconnect Networks Switches Virtual Channels +12 more Show less

Verilog SystemVerilog UVM SVA VCS Perl Tcl Makefiles Python LLMs Agentic AI frameworks VCS-XA Gate Level Simulation Formal Equivalence +9 more Show less

Perl TCL Make Python RTL Logic Synthesis Equivalence Checking Clock Domain Crossing Checks MTBF Analysis Static Timing Analysis Timing Constraints Management EDA Tools DFT Timing Closure AI Utilization +9 more Show less

Verilog System-Verilog Python Perl Tcl Makefiles CDC checks Formal equivalence RTL design Synthesis Timing analysis DFT ATE test development Post-si bringup Debugging Behavioral real number modeling Mixed signal design Custom designed IPs Agentic AI flows +14 more Show less

Verilog SystemVerilog Perl Python VCS Verdi GDB Random Stimulus Functional Coverage Assertion-Based Verification Logic Synthesis Timing Analysis Embedded Processors +8 more Show less

SystemVerilog UVM VCS Verdi Perl Python C++ UPF DFT Machine_Learning ASIC_design_flow +6 more Show less

Verilog RTL ASIC VLSI Digital systems Computer Architecture Computer Arithmetic Low-power design Logic synthesis Timing analysis Arbiters Scheduling Synchronization Bus protocols Interconnect networks Dataflow architectures CPU subsystems +12 more Show less

Verilog RTL C C++ Python Perl VLSI Computer_Architecture Digital_Systems Logic_Synthesis Timing_Analysis +6 more Show less

Verilog RTL Python Perl C C++ PCI-Express CXL ASIC VLSI Digital systems Computer Architecture CMOS transistors and circuits DFT timing analysis floor-planning ECO bring-up & lab debug arbiters synchronization bus protocols interconnect networks caches +18 more Show less

Innovus ICC2 PrimeTime Calibre Pegasus ICV TCL Python Perl SDC UPF CPF CLP SerDes DDR PCIe FinFET EM/IR Thermal-aware clocking Reliability modeling RTL-to-GDS Flow Virtuoso +17 more Show less