Senior ASIC Floorplan Design Engineer

What you'll do

• Develop and optimize floorplans for SoCs and GPUs during early chip development.
• Drive area review processes to identify improvements in interconnect and floorplan design.
• Solve timing and routing congestion issues by influencing early design decisions.
• Build tools and enhance infrastructure to optimize chip area and speed execution.
• Collaborate with architects, design leads, and physical design teams for optimization.

What we're looking for

• Master’s degree in Electrical Engineering, Computer Science, or related field.
• 12+ years of experience in VLSI and/or computer architecture.
• Expertise in Verilog, System Verilog, and other hardware verification languages.
• Proficiency in CAD methodologies, chip floorplanning, power/clock distribution.
• Experience with physical design tools and processes (P&R, timing closure).
• Strong communication skills and ability to work effectively in a team.
• Knowledge of Python, Perl, and C/C++ programming languages.