Senior ASIC Floorplan Design Engineer

Nvidia

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TX
Salary: $196,000–$310,500 / yr
Employment: Full-time
Posted: 159 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $253k

$129k $330k

below market most similar roles pay here above market

This role pays more than 94% of similar roles. Most pay $170,527–$216,250 — the blue band above. At the midpoint, this role pays about $253k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Floorplan Design Engineer

Role Posting Log in to save

The Senior ASIC Floorplan Design Engineer joins a global team to design and implement leading SoCs and GPUs. In this role, you will collaborate with architects and design leads to craft and optimize floorplans during early chip development. Your daily responsibilities include driving the area review process, identifying interconnect improvement opportunities, and solving timing and routing congestion issues through early design decisions. You will also build tools and improve infrastructure to optimize chip area and execution speed. Required skills include a deep hardware engineering background in VLSI or Computer Architecture, proficiency in Verilog and System Verilog, and experience with CAD and physical design methodologies. You must also possess programming experience in Python, Perl, and C/C++ to support the development of high-performance computing hardware.

Skills

ASIC Floorplan Design VLSI Computer Architecture Verilog System Verilog Python Perl C/C++ CAD Physical Design P&R Timing Closure Power/Clock Distribution Packaging

What you'll do

Develop and optimize floorplans during the early stages of chip development.
Drive the area review process to identify improvement opportunities for area and interconnects.
Solve timing and routing congestion issues by influencing early design and physical implementation decisions.
Build new tools and improve existing infrastructure to optimize chip area and execution speed.
Manage power and clock distribution and packaging requirements for large-scale ASICs.
Ensure timing closure through close coordination with physical design and ASIC design teams.

What we're looking for

Master's Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
12+ years of relevant work experience.
Deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
Experience in Verilog, System Verilog, or similar HVL.
Experience with CAD and physical design methodologies, chip floorplan, power/clock distribution, packaging, P&R, and timing closure.
Proficiency in Python, Perl, and C/C++ programming languages.
Strong communication and interpersonal skills.
Experience in driving development of large scale ASIC floorplan (preferred).

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