Senior ASIC Floorplan Design Engineer

Nvidia

Confirmed live 2 days ago Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$196,000–$310,500 / yr
Posted
113 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $253k
$131k most similar roles pay here $330k

This role pays more than 90% of similar roles. Most pay $174,843–$216,250 — the shaded band above. At the midpoint, this role pays about $253k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior ASIC Floorplan Design Engineer

Role Posting Log in to save

As a Senior ASIC Floorplan Design Engineer, you will join the team to design and implement leading SoCs and GPUs. You will collaborate with architects, design leads, physical design leads, and package leads to craft and optimize floorplans during early chip development stages. Your daily responsibilities include driving the area review process, identifying improvements for interconnects and floorplans, and solving timing and routing congestion issues through influenced design decisions. Additionally, you will build tools and improve infrastructure to optimize chip area and execution speed. The role requires expertise in Verilog, SystemVerilog, Python, Perl, and C/C++. You must possess a deep background in VLSI and Computer Architecture, with specific experience in CAD methodologies, power and clock distribution, packaging, P&R, and timing closure to address complex hardware engineering challenges within the GPU and SoC product space.

Skills

ASIC Floorplan VLSI Computer Architecture Verilog System Verilog Python Perl C/C++ CAD Physical Design Timing Closure Clock Distribution Packaging

What you'll do

  • Develop and optimize floorplans during the early stages of chip development.
  • Drive the area review process to identify improvements in layout and interconnects.
  • Resolve timing and routing congestion issues through early design and physical implementation decisions.
  • Build new tools and improve existing infrastructure to optimize chip area and execution speed.
  • Manage power and clock distribution across the SoC floorplan.
  • Implement complex floorplans for large-scale GPUs and SoCs.

What we're looking for

  • Master's degree in Electrical Engineering, Computer Science, or Computer Engineering is required or equivalent experience.
  • 12+ years of relevant work experience are required.
  • A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture is required.
  • Experience in Verilog, SystemVerilog, or similar Hardware Verification Languages (HVL) is required.
  • Experience with CAD and physical design methodologies including floorplan, power/clock distribution, packaging, P&R, and timing closure is required.
  • Proficiency in Python, Perl, and C/C++ programming languages is required.
  • Strong communication and interpersonal skills are required to work effectively as a teammate.

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