Senior ASIC Design Engineer

Nvidia

Confirmed live today Low trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Employment: Full-time
Posted: 78 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $192k

$136k $232k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $167,737–$216,250.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer

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The Senior ASIC Design Engineer joins the design team to build and implement leading SoCs and GPUs for consumer graphics, self-driving cars, and artificial intelligence. This role focuses on the micro-architecture and build implementation of GPU memory systems units, including caches, coherency, complex pipelines, arbiters, and interconnect networks. You will micro-architect features to meet specific area, performance, and power requirements while delivering fully verified, synthesis, and timing clean builds. Key responsibilities involve collaborating with architects, verification engineers, software engineers, and physical build engineers. Required skills include proficiency in logic design, Verilog, and System-Verilog, with a deep understanding of Computer Architecture and ASIC flows like RTL, logic synthesis, and timing analysis. Candidates should also possess experience with AI workflows and autonomous agents for design methodologies.

What does a ASIC Design Engineer earn in California?

Median $214000 from 49 postings across 7 companies.

See salary data

Skills

ASIC Design Verilog System-Verilog RTL Logic Synthesis Timing Analysis Computer Architecture GPU ECO Micro-architecture Interconnect Networks Caches Coherency AI Workflows Tapeout Debugging

What you'll do

Design and implement micro-architecture for GPU memory systems units including caches and interconnect networks.
Micro-architect features to meet specific area, performance, and power requirements.
Develop RTL for complex IPs from initial inception through final tapeout.
Deliver a fully verified build in coordination with verification engineers.
Provide a synthesis and timing clean build to ensure a routable and physically implementable design.
Implement logic for arbiters, shared buffers, virtual channels, and deadlock avoidance policies.
Utilize AI workflows and autonomous agents to enhance design methodologies.

What we're looking for

Bachelor's or Master's Degree in Electrical Engineering or Computer Engineering, or equivalent experience.
8+ years of experience delivering design/RTL for complex IPs from inception through tapeout.
Prior experience building arbiters, shared buffers, virtual channels, interconnection routing policies, and deadlock avoidance.
High proficiency in logic design, Verilog, and/or SystemVerilog with a solid understanding of Computer Architecture.
Deep understanding of ASIC flow including RTL, verification, logic synthesis, timing analysis, and ECO.
Proficiency in developing/using AI workflows and/or autonomous agents for design methodologies.
Strong interpersonal and communication skills to collaborate across teams.
Good debugging and analytical skills.

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