Senior ASIC Design Engineer

Nvidia

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
17 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $187k
This role $216k
$127k most similar roles pay here $279k

This role pays more than 78% of similar roles. Most pay $158,512–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer

NVIDIA seeks a Senior ASIC Design Engineer to join its dynamic team focused on developing cutting-edge SoCs and GPUs for applications ranging from consumer graphics to autonomous vehicles. In this role, you will micro-architect features and build implementation of NOC/interconnect Xbar, ensuring they meet stringent area, performance, and power requirements while collaborating closely with verification engineers to deliver a fully verified design. You will also work on synthesis/timing clean builds for physical implementability, engaging with architects, software engineers, and physical designers to achieve project goals. Ideal candidates possess 8+ years of experience in complex unit build/RTL, proficiency in Verilog/System-Verilog, and a deep understanding of ASIC flow including RTL design, verification, logic synthesis, timing analysis, ECO, and post-silicon debug.

What you'll do

  • Design and implement NOC/interconnect Xbar micro-architecture to meet performance goals.
  • Ensure area, power, and performance requirements are met for ASIC design.
  • Work closely with verification engineers to deliver a fully verified build.
  • Create synthesis/timing clean builds for routable and physically implementable designs.
  • Collaborate on the implementation of arbitration policies and interconnection routing.

What we're looking for

  • Bachelor's or Master’s Degree in Electrical/Computer Engineering or equivalent experience.
  • 8+ years of RTL design experience on complex units like xbar/memory systems.
  • Proficiency in Verilog/SystemVerilog and deep understanding of ASIC flow processes.
  • Strong collaboration skills for working across multiple engineering disciplines.
  • Experience building arbiters, scheduling mechanisms, synchronization protocols.

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