Senior ASIC Design Engineer

Nvidia

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
32 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $216k
$132k most similar roles pay here $279k

This role pays more than 80% of similar roles. Most pay $172,000–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Design Engineer

Role Posting Log in to save

As a Senior ASIC Design Engineer, you will join the design team to build and implement leading SoCs and GPUs for applications including consumer graphics, self-driving cars, and artificial intelligence. You will be responsible for the micro-architecture and build implementation of GPU memory systems units such as caches, coherency, complex pipelines, arbiters, or interconnect networks. Your daily work involves micro-architecting features to meet area, performance, and power requirements while delivering synthesis and timing clean builds. You will collaborate with architects, verification engineers, software engineers, and physical build engineers. The role requires expertise in Verilog, SystemVerilog, and Computer Architecture, along with experience in RTL, logic synthesis, timing analysis, and ECO. You must possess skills in building arbiters, shared buffers, virtual channels, and interconnection routing policies while utilizing AI workflows for design methodologies.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

Verilog System-Verilog ASIC Design RTL Logic Synthesis Timing Analysis Computer Architecture GPU Memory Systems Interconnect Networks ECO AI Workflows Autonomous Agents

What you'll do

  • Design and implement micro-architecture for GPU memory systems including caches, coherency, pipelines, arbiters, and interconnect networks.
  • Optimize micro-architectural features to meet specific area, performance, and power requirements.
  • Deliver a fully verified build by coordinating with verification engineers.
  • Provide synthesis and timing clean builds to ensure routable and physically implementable designs.
  • Develop RTL for complex IPs from inception through tapeout using Verilog or SystemVerilog.
  • Implement arbitration logic, shared buffers, virtual channels, and deadlock avoidance routing policies.
  • Utilize AI workflows and autonomous agents to enhance design methodologies.

What we're looking for

  • Bachelor's or Master’s Degree in Electrical Engineering or Computer Engineering, or equivalent experience.
  • 8+ years of experience delivering design/RTL for complex IPs from inception through tapeout.
  • Experience building arbiters, shared buffers, virtual channels, and interconnection routing policies/deadlock avoidance.
  • Proficiency in logic design, Verilog, and/or SystemVerilog with a solid understanding of Computer Architecture.
  • Deep understanding of ASIC flow including RTL, verification, logic synthesis, timing analysis, and ECO.
  • Proficiency in developing or using AI workflows and autonomous agents for design methodologies.
  • Strong interpersonal and communication skills to collaborate across multiple teams.
  • Good debugging and analytical skills.

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