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Active Keyword: ASIC Design Engineer Remove filter Location: San Diego Remove filter Clear all

20 of up to 20 (filtered)

ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm

San Diego, CA 3 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Posted this week High trust Below market
RTL ASIC Design SerDes DDR PCIe USB UFS MIPI VCS Fusion Compiler PrimeTime Power Compiler Spyglass Python Perl DFT STA CDC GDSII
4+ yrs exp
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High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 8 days ago $140,000–$229,800
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture
4+ yrs exp
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Senior Design Verification Engineer

Qualcomm

San Diego, CA 21 days ago $115,600–$173,400
Actively hiring Confirmed live 2 days ago Trusted Below market
SystemVerilog UVM Verilog VHDL Python C++ Perl Formal Verification UPF AMBA AXI AHB APB RTL Object-Oriented Programming Scripting Automation
2+ yrs exp
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Digital ASIC Design Engineer

Qualcomm

San Diego, CA 23 days ago $98,500–$147,700
Actively hiring Confirmed live yesterday Trusted Below market
ASIC RTL Design Verilog System Verilog VHDL Python Perl SoC Logic Design System Simulation Clock Design
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Analog/Mixed Signal ASIC Design Engineer

Qualcomm

San Diego, CA 28 days ago $98,500–$147,700
Actively hiring Confirmed live yesterday High trust Below market
CMOS Mixed Signal Design Cadence ADE MATLAB SPICE Verilog VHDL PLL SERDES 5G Analog Design Automation Layout Silicon Evaluation
2+ yrs exp
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High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 30 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Trusted Below market
ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture
4+ yrs exp
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ASIC Design Engineer

Qualcomm

San Diego, CA 32 days ago $98,500–$147,700
Actively hiring Confirmed live yesterday Trusted Below market
ASIC SoC RTL Design Static Timing Analysis Synthesis Verification Silicon Bring-up Python Tcl Perl FPGA Low-power Design IP Integration System Simulation Automation
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High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 37 days ago $140,000–$210,000
Actively hiring Confirmed live 2 days ago Trusted Below market
ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture
4+ yrs exp
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ASIC Digital Design Engineer Lead

Apple Inc

San Diego, CA 42 days ago $166,600–$296,000
Actively hiring Confirmed live yesterday Trusted Above market
Digital Design FPGA Silicon Bring-up Characterization Debug Mixed Signal Design MIPI HDMI TCON Micro-architecture Emulation Verification
10+ yrs exp
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Analog/Mixed Signal ASIC Design Engineer

Qualcomm

San Diego, CA 43 days ago $142,400–$213,600
Actively hiring Confirmed live yesterday High trust Competitive pay
Cadence Virtuoso ASIC Design SerDes DDR PLL DAC ADC Python MATLAB SPICE Verilog VHDL Circuit Simulation Schematic Capture FinFET CMOS
2+ yrs exp
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Design Verification Engineer

Qualcomm

San Diego, CA 43 days ago $115,600–$173,400
Actively hiring Confirmed live yesterday Trusted Below market
SystemVerilog UVM Verilog VHDL Python C++ Perl Formal Verification UPF AMBA AXI AHB APB RTL Object-Oriented Programming Scripting Automation
2+ yrs exp
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Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 43 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Low trust Below market
Verilog SystemVerilog ASIC Design RTL Synopsys Synthesis Low Power Design Computer Architecture C C++ Python Design Verification SOC Interconnects Memory Subsystems
4+ yrs exp
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Digital ASIC Design Engineer for Mixed-Signal IPs

Qualcomm

San Diego, CA 71 days ago $115,600–$173,400
Actively hiring Confirmed live 2 days ago Trusted Below market
RTL ASIC Design Mixed-Signal IP Digital Signal Processing VCS Fusion Compiler PrimeTime Power Compiler Spyglass DFT STA CDC Python Perl GDSII Synthesis Formal Verification Floorplanning Pre-silicon Simulation
2+ yrs exp
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ASIC Design Verification Engineer

Amazon Inc

Austin, TX +3 78 days ago $136,000–$184,000
Actively hiring Confirmed live 2 days ago High trust Below market
UVM SystemVerilog Verilog SystemC Matlab C DPI-C Formal Verification RTL ASIC Digital Verification Scripting CMOS
5+ yrs exp
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Senior ASIC Design Engineer

Amazon Inc

San Diego, CA 78 days ago $159,200–$215,300
Actively hiring Confirmed live 2 days ago High trust Above market
ASIC Design RTL UVM System C DPI-C Matlab Formal Verification DFT Low Power Design CMOS Digital Design Verification Test Bench
7+ yrs exp
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ASIC Design Engineer I, Satellite Communications

Amazon Inc

San Diego, CA 78 days ago $122,600–$170,000
Actively hiring Confirmed live yesterday High trust Below market
ASIC RTL DSP MATLAB UVM System C DPI-C Digital Logic Design CMOS Micro-architecture Bus Fabrics Communication Systems
2+ yrs exp
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Lead ASIC Design Verification Engineer

Amazon Inc

Sunnyvale, CA +2 78 days ago $159,200–$215,300
Actively hiring Confirmed live yesterday High trust Above market
UVM C++ C Matlab Formal Verification System C DPI-C RTL FPGA Emulation Scripting ASIC Design Digital Verification CMOS
7+ yrs exp
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Senior ASIC Design Verification Engineer

Amazon Inc

Sunnyvale, CA +1 78 days ago $159,200–$215,300
Actively hiring Confirmed live 2 days ago High trust Above market
UVM C++ C System C DPI-C Formal Verification Matlab RTL FPGA Emulation Digital Verification ASIC Scripting CMOS
7+ yrs exp
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Analog/Mixed Signal ASIC Design Engineer

Qualcomm

San Diego, CA 93 days ago $142,400–$213,600
Actively hiring Confirmed live 2 days ago High trust Competitive pay
Cadence Virtuoso ASIC Design SerDes PLL DAC ADC Matlab Python SPICE Verilog VHDL CMOS FinFET Signal Processing Schematic Capture
2+ yrs exp
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Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 126 days ago $127,200–$190,800
Actively hiring Confirmed live 2 days ago Trusted Below market
RTL system Verilog Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Clock Domain Crossing Microprocessor Design Bus Interface Cache Linting LEC CLP GDS2 Synthesis
2+ yrs exp
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