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UVM System C C++ C Matlab Formal Verification DPI-C RTL FPGA Emulation DSP Scripting +7 more Show less

ASIC Design RTL SoC UVM System C DPI-C Python Perl DSP ARM DFT Synthesis Timing Analysis NoC CMOS Low Power Design +11 more Show less

ASIC Design RTL Design SystemVerilog Verilog Computer Architecture Synopsys Synthesis Low Power Design Python C++ C Coverage-based Design Verification SoC Interconnects Memory Controllers micro architecture Debugging +10 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting +3 more Show less

UVM C/C++ Formal Verification Matlab System C DPI-C RTL FPGA Emulation Scripting DSP CMOS +7 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting Logic Design +4 more Show less

Verilog SystemVerilog RTL Design Synopsys Synthesis Python C++ C Computer Architecture Low Power Design Coverage-based Design Verification OpenGL Vulkan Direct3D ASIC GPU DSP Machine-Learning +12 more Show less

ASIC Design RTL Micro-architecture SerDes DDR Mixed-Signal IP VCS Fusion Compiler PrimeTime Power Compiler Spyglass DFT Static Timing Analysis Formal Verification Python Perl Digital Signal Processing PCIe USB UFS MIPI +16 more Show less

ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture +12 more Show less

CMOS Mixed Signal Design Cadence ADE MATLAB SPICE Verilog VHDL FinFET 5G PLL SERDES Layout Analog Design Automation +8 more Show less

ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture +11 more Show less

SystemVerilog UVM Verilog VHDL Python C++ C Perl Formal Verification UPF AMBA AXI AHB APB ASIC Design RTL Object-oriented programming Automation +13 more Show less

Cadence Virtuoso SPICE Python Matlab Verilog VHDL ASIC Design Mixed Signal Design Analog Circuit Design SerDes DDR PLL DAC ADC FinFET CMOS Signal Processing +12 more Show less

Cadence Virtuoso ASIC Design Python Matlab SPICE Verilog VHDL Mixed-Signal Design CMOS FinFET SerDes PLL DAC ADC Signal Processing Schematic Capture +11 more Show less

ASIC Design Verilog system-verilog RTL Design SoC Digital Design Synthesis Timing Closure DFT Clock Domain Crossings AHB AXI Root of Trust Cryptography Error Correction Codes Silicon Testing Microarchitecture +12 more Show less

Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture +9 more Show less

ASIC Design RTL SoC UVM System C DPI-C Python Perl DFT Synthesis Timing Analysis ARM DSP NoC Formal Verification CMOS 4G 5G DVB-S2 DVB-C +15 more Show less

Digital Design FPGA Emulation Silicon Bring-up Characterization Debug Mixed Signal Design MIPI HDMI Micro-architecture Verification Emulation TCON Display Pipeline +8 more Show less

SystemVerilog UVM Verilog SystemC Matlab C DPI-C Formal Verification RTL DSP CMOS Scripting +7 more Show less

ASIC Design RTL UVM System C DPI-C DFT Formal Verification Matlab CMOS Low Power Design Digital Design Verification Test Bench +7 more Show less