ASIC Design Engineer, Hardware Security

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CASanta Clara, CA
Salary
$140,000–$229,800 / yr
Posted
128 days ago
Freshness
Confirmed live yesterday
Closes
Nov 2, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $189k
This role $185k
$129k most similar roles pay here $241k

This role pays less than 52% of similar roles. Most pay $162,000–$215,537 — the shaded band above. At the midpoint, this role pays about $185k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Hardware Security

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The ASIC Design Engineer (Hardware Security) joins the Hardware Security team to develop cutting-edge security solutions for premium Snapdragon chipsets. This high-profile role involves collaborating with cross-functional teams across the entire hardware security product creation flow, including architecture, microarchitecture, design, validation, IP development, synthesis, timing closure, layout, and silicon testing. The candidate will work on state-of-the-art security solutions, countermeasures, and techniques. Essential technical skills include experience in Verilog/SystemVerilog RTL design, clock domain crossings, DFT, and knowledge of bus protocols, clocks, resets, and debug concepts. Preferred expertise includes microcontroller CPUs, AXI/AHB buses, high-speed low-power architecture, and specific security domains such as Root of Trust, RNG, symmetric and asymmetric crypto, side-channel protections, and error correction codes. The role addresses critical hardware security challenges within the mobile and connected device ecosystem.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

ASIC Verilog system-verilog RTL Design SoC DFT Synthesis Timing Closure AHB AXI Root of Trust Cryptography Error Correction Codes Silicon Testing Digital Design Microarchitecture

What you'll do

  • Design and develop hardware security solutions for premium Snapdragon chipsets.
  • Execute the full ASIC design flow including architecture, microarchitecture, and RTL design using Verilog or SystemVerilog.
  • Manage technical aspects of the design cycle such as synthesis, timing closure, and layout.
  • Implement advanced security countermeasures, including Root of Trust, RNG, and cryptographic protections.
  • Integrate complex subsystems and manage high-speed, low-area, and low-power architectures.
  • Perform silicon testing and validation to ensure hardware reliability and performance.
  • Resolve complex technical issues related to bus protocols, clock domains, and debug concepts.

What we're looking for

  • Bachelor's degree in electrical engineering or a related science field is required.
  • A Master's degree or PhD in a relevant field is preferred.
  • Candidates must have 6+ years of experience in ASIC design with a Bachelor's degree.
  • Candidates with a Master's degree require 5+ years of experience in ASIC design, verification, or validation.
  • Candidates with a PhD require 4+ years of experience in ASIC design, verification, or validation.
  • Experience must include ASIC design flow including architecture, microarchitecture, Verilog/SystemVerilog RTL design, and timing closure.
  • Knowledge of bus protocols, clock domain crossings, DFT, synthesis, and debug concepts is required.
  • Preferred skills include hardware security fields like Root of Trust, crypto, side-channel analysis, and low power architecture.

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