Analog/Mixed Signal ASIC Design Engineer

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$142,400–$213,600 / yr
Posted
5 days ago
Closes
Dec 7, 2026

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $182k
This role $178k
$123k most similar roles pay here $247k

This role pays more than 53% of similar roles. Most pay $155,000–$208,350 — the shaded band above. At the midpoint, this role pays about $178k versus about $182k for comparable roles.

Based on 239 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 749 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.

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At a glance

TL;DR · Analog/Mixed Signal ASIC Design Engineer

The QCT mixed-signal IP design team seeks an Analog/Mixed Signal ASIC Design Engineer to contribute to the development of advanced mixed-signal IPs including SerDes, DDR, PLLs, DACs, ADCs, and sensors for cutting-edge applications in 5G, AI/ML, compute, and automotive sectors. The role involves schematic capture and simulations using Cadence Virtuoso, participating in architecture definition, collaborating with layout and digital teams, and working closely with testing teams to ensure successful silicon bringup and debugging. Ideal candidates hold a Master's degree in Electrical Engineering or a related field, possess experience with ASIC design tools like Cadence Virtuoso, and have several years of industry experience in high-speed analog circuit design for mixed-signal IPs. Additional skills include proficiency in Matlab and Python, understanding of sampled domain signal processing, and knowledge of yield optimization and production challenges associated with high-speed serial links.

What you'll do

  • Conduct schematic capture and simulations using Cadence Virtuoso.
  • Define architecture and analog/digital design partitioning in mixed-signal IPs.
  • Collaborate with layout teams for physical implementation of designs.
  • Work closely with testing team to bring up silicon and debug issues.
  • Design high-speed, low-power mixed-signal IPs like SerDes, PLLs, ADCs.

What we're looking for

  • Master's degree in Electrical Engineering or related field.
  • Experience with Cadence Virtuoso for schematic capture and simulations.
  • Industry experience in analog integrated circuit/system design.
  • High-speed analog designer experience with mixed-signal IPs like CTLE, CDR, PLL.
  • Familiarity with Matlab and Python for system integration aspects.
  • Understanding of design for yield and production challenges in high-speed links.

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