Analog/Mixed Signal ASIC Design Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $145,600–$218,400 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $208k

This role $182k

$134k $257k

below market most similar roles pay here above market

This role pays less than 62% of similar roles. Most pay $173,375–$241,750 — the blue band above. At the midpoint, this role pays about $182k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Analog/Mixed Signal ASIC Design Engineer

Role Posting Log in to save

The Analog/Mixed Signal ASIC Design Engineer joins the mixed-signal IP design team to develop high-speed, high-performance, and low-power mixed-signal IPs. This role involves schematic capture, simulations, architecture definition, and analog/digital design partitioning for products targeting 5G, AI/ML, compute, and automotive applications. The engineer will work on components such as SerDes, DDR, PLL, DAC, ADC, and sensors. Key responsibilities include collaborating with layout, digital, and testing teams for silicon bringup and debugging. Required technical skills include proficiency with the Cadence Virtuoso tool suite, SPICE, MATLAB, and Python. Candidates must demonstrate expertise in analog integrated circuit design, specifically regarding nanometer planar CMOS or FinFET technologies, while addressing design for yield and production challenges for high-speed serial links and sampled domain signal processing.

Skills

Cadence Virtuoso ASIC Design Python Matlab SPICE Verilog VHDL Mixed-Signal Design CMOS FinFET SerDes PLL DAC ADC Signal Processing Schematic Capture

What you'll do

Perform schematic capture and simulations using the Cadence Virtuoso tool suite.
Participate in architecture definition and analog/digital design partitioning.
Design high-speed, high-performance, and low-power mixed-signal IPs like SerDes, DDR, and PLLs.
Coordinate with layout and digital teams to ensure seamless integration.
Work with testing teams to perform silicon bringup and hardware debugging.
Address design for yield and production challenges for high-speed serial links.

What we're looking for

Master's degree in Electrical Engineering or related field.
Bachelor's degree in Electrical Engineering with 2+ years of experience in analog or mixed-signal integrated circuit design and 4+ years of ASIC design experience.
PhD in Electrical Engineering or related field and 2+ years of ASIC design, verification, or related work experience.
2+ years of experience using one or more design tools such as CADENCE, SPICE, MATLAB, and/or Verilog/VHDL.
Experience working with ASIC design tools such as Cadence Virtuoso.
Demonstrated interest in analog circuit design by course selections and/or work experience.
Several years of industry experience in the area of analog integrated circuit/system design (preferred).
Experience as a high speed analog designer of mixed-signal IPs such as CTLE, CDR, PLL, DAC, or ADC (preferred).

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