This role pays less than
60%
of similar roles. Most pay
$175,000–$217,500
— the shaded band above.
At the midpoint, this role pays about
$178k
versus about
$196k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
623 open roles
on FindRole.
Listed pay typically runs
$148,300–$222,500
across 603 roles with salary data.
The Analog/Mixed Signal ASIC Design Engineer joins the mixed-signal IP design team to develop high-speed, high-performance, and low-power mixed-signal IPs for 5G, AI/ML, compute, and automotive applications. The role involves performing schematic capture and simulations using the Cadence Virtuoso tool suite while participating in architecture definition and analog/digital design partitioning. You will collaborate with cross-functional layout and digital teams and work with testing teams for silicon bringup and debugging. Key technical requirements include experience with Cadence Virtuoso, SPICE, MATLAB, Python, and Verilog/VHDL. The position focuses on designing critical components such as SerDes, DDR, PLL, DAC, ADC, and sensors. Candidates should possess a strong understanding of signals and systems, sampled domain signal processing, and design for yield challenges associated with high-speed serial links in nanometer planar CMOS or FinFET technologies.
Perform schematic capture and simulations using the Cadence Virtuoso tool suite.
Participate in architecture definition and analog/digital design partitioning for mixed-signal IPs.
Design high-speed, high-performance, and low-power mixed-signal circuits including SerDes, DDR, PLL, DAC, and ADC.
Support silicon bringup and debugging activities in coordination with the testing team.
Address design for yield and production challenges specifically related to high-speed serial links.
Develop mixed-signal IP designs targeted for 5G, AI/ML, compute, and automotive applications.
What we're looking for
A Bachelor's degree in Electrical Engineering with 2+ years of experience in analog or mixed-signal IC design and 4+ years of ASIC design/verification experience.
A Master's degree in Electrical Engineering or a related field with 4+ years of ASIC design, verification, or related work experience.
A PhD in Electrical Engineering or a related field with 2+ years of ASIC design, verification, or related work experience.
Experience using design tools such as Cadence Virtuoso, SPICE, MATLAB, and/or Verilog/VHDL.
Demonstrated interest in analog circuit design through relevant coursework or professional experience.
Experience designing high-speed mixed-signal IPs such as CTLE, CDR, PLL, DAC, or ADC.
Proficiency in Matlab and Python with an understanding of system integration for mixed-signal designs.
Knowledge of signals and systems, sampled domain signal processing, and design for yield/production challenges.