Next-Gen High-Speed HBM LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $145,600–$218,400 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k

This role $182k

$134k $257k

below market most similar roles pay here above market

This role pays less than 61% of similar roles. Most pay $167,137–$227,500 — the blue band above. At the midpoint, this role pays about $182k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Next-Gen High-Speed HBM LPDDR Memory Subsystem ASIC Digital Design Engineer

Role Posting Log in to save

Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer The Senior ASIC Design Engineer joins the Next Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team. This role involves the architecture, RTL coding, and deployment of high-speed memory subsystems into products. Key responsibilities include developing architecture specifications, driving micro-architecture for logic design, implementing RTL, and performing synthesis, timing closure, physical design support, gate level simulations, and power analysis. The engineer must debug designs and provide integration support for components interfacing with CPUs, GPUs, DSPs, and multimedia processors. Required skills include ASIC design, RTL coding, and hardware architecture experience. Technical domain context includes LPDDR memory, cache controllers, NoC-based architectures, HBM memory types, on-chip SRAM, L3 cache controllers, and x86 or ARM CPU/bus architectures.

Skills

ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture

What you'll do

Develop architecture and design specifications for next-generation high-speed memory subsystems.
Drive the micro-architecture for specific portions of the logic design.
Implement and deliver high-quality RTL code for memory controllers and NoCs.
Debug designs and provide technical support when integrated into the rest of the chip.
Perform synthesis, timing closure, and physical design support tasks.
Conduct gate level simulations and power analysis for high-speed designs.
Contribute to improvements in design methodology to increase productivity and quality.

What we're looking for

Bachelor's degree in Science, Engineering, or related field.
Master's degree in Computer Engineering or Electrical Engineering (preferred).
5+ years of ASIC design, RTL coding, and front-end digital design experience.
3+ years of Hardware Architecture experience.
4+ years of ASIC design, verification, validation, or integration experience with a Bachelor's degree (or 3+ years with a Master's).
Experience with LPDDR memory, cache controllers, and NoC based architectures (preferred).
Experience with x86 or ARM CPU/bus architectures (preferred).
Exposure to HBM memory type designs (preferred).

Similar roles

Next-Gen High-Speed HBM LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400

ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture

4+ yrs exp

Save

Next-Gen High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400

Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture

4+ yrs exp

Save

Next-Gen System Cache ASIC Digital Design Engineer

Qualcomm

San Diego, CA 20 days ago $121,800–$182,600

ASIC Design RTL Design SystemVerilog Verilog Computer Architecture Synopsys Synthesis Low Power Design Python C++ C Coverage-based Design Verification SoC Interconnects Memory Controllers micro architecture Debugging

2+ yrs exp

Save

Senior ASIC Design Engineer, Memory Subsystem

Nvidia

Santa Clara, CA 14 days ago $136,000–$218,500

ASIC Design RTL Design Verilog VHDL Synthesis Timing Analysis CHI CXL PCI-E PERL CAD Tools Hardware-managed Coherency System Level Caches Protocol Bridges Asynchronous Interfaces

5+ yrs exp

Save

Senior RTL Design Engineer, DDR/LPDDR Memory Controller

Amd

Austin, TX +2 109 days ago $178,400–$267,600

RTL Design Verilog SystemVerilog Python Perl Tcl Digital Logic Design Computer Architecture DDR LPDDR EDA Tools Lint CDC Timing Analysis Synthesis Simulation IP Microarchitecture

Save

Next Gen High-Speed Memory and Cache Controller Design Engineer

Qualcomm

San Diego, CA 20 days ago $101,400–$152,200

ASIC Design RTL LPDDR HBM DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Physical Design Micro-architecture ISA

3+ yrs exp

Save