Graphics ASICS Hardware Design Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: San Diego, CASanta Clara, CAAustin, TXBoxborough, MA
Salary: $203,700–$305,500 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k

This role $255k

$132k $324k

below market most similar roles pay here above market

This role pays more than 88% of similar roles. Most pay $166,175–$227,300 — the blue band above. At the midpoint, this role pays about $255k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Graphics ASICS Hardware Design Engineer

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The Graphics ASICS Hardware Design Engineer joins the GPU ASICS Engineering team to develop Adreno GPU architecture for Snapdragon compute platforms. This role involves micro-architecting and designing RTL for various blocks, including shader processing, graphics pipelines, memory subsystems, interconnects, and power systems. Key responsibilities include evaluating hardware feasibility for complex algorithms, developing specifications for new generation designs, and performing verification and debugging throughout the project cycle. The engineer must optimize silicon cost, improve clock speed, and troubleshoot silicon issues. Required technical skills include Verilog, SystemVerilog, Synopsys synthesis, low power design, and coverage-based design verification. Desired competencies include Computer Architecture, C/C++, Python, and experience with GPU, CPU, or DSP blocks. The work focuses on solving hardware performance, power, and cost challenges for mobile, PC, and automotive solutions.

Skills

Verilog SystemVerilog RTL Design Synopsys Synthesis Python C++ C Computer Architecture Low Power Design Coverage-based Design Verification OpenGL Vulkan Direct3D ASIC GPU DSP Machine-Learning

What you'll do

Micro-architect and design RTL for Adreno GPU blocks including shader processing and memory subsystems.
Develop micro-architecture specifications for new generation GPU designs.
Evaluate hardware feasibility for complex algorithms and technical requirements.
Optimize hardware design for improved performance, power efficiency, and silicon cost.
Provide verification and debugging activities for designs throughout the entire project cycle.
Troubleshoot silicon issues for products relevant to the assigned design.
Improve clock speeds and optimize overall silicon cost.

What we're looking for

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 6+ years of relevant work experience.
Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 5+ years of relevant work experience.
PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of relevant work experience.
Experience with Verilog/SystemVerilog design, Synopsys synthesis, low power design, test plan development, and coverage-based design verification.
Experience with Computer Architecture, Computer Arithmetic, Low power design, and C/C++/Python programming languages (preferred).
Experience in designing RTL for GPU, CPU, DSP, Machine-Learning, cache, controller, video, display, or camera blocks in ASIC (preferred).
Exposure to Graphics API (OpenGL, Vulkan, Direct3D, etc.) (preferred).
Good communication skills and a desire to work as a team player.

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