Senior ASIC Design Engineer

Amazon Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $159,200–$215,300 / yr
Posted: 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $182k

This role $187k

$135k most similar roles pay here $224k

This role pays more than 67% of similar roles. Most pay $161,500–$201,525 — the shaded band above. At the midpoint, this role pays about $187k versus about $182k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 321 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 304 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Engineer

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As a Senior ASIC Design Engineer at Amazon Leo in the Hardware Development team, you will be responsible for implementing wireless system architecture from specification to chip-level validation. Your daily tasks include optimizing timing and power while ensuring high-quality designs meet customer experience goals such as throughput and latency. You will develop standalone verification test benches using UVM and System C, collaborate with the verification team on system-level verification, and work closely with the implementation team to ensure DFT, timing, and power targets are met. Familiarity with low-power design techniques and space systems is essential, along with experience in digital design for communication systems and products that have reached volume production. Preferred candidates will also be proficient in UVM, Matlab, and formal verification methods.

Skills

UVM Matlab SystemC DPI-C Verilog VHDL RTL Python CI/CD AWS Linux Git SVN JIRA Confluence

What you'll do

Implement wireless system architecture from specification to chip validation.
Optimize customer experience throughputs and latency while meeting power constraints.
Develop high-quality silicon solutions for first-time right designs.
Create standalone verification test benches using UVM, System C, and DPI-C.
Collaborate with implementation teams to ensure DFT, timing, and power targets.

What we're looking for

7+ years of experience in digital design, preferably in communication systems.
Experience with products that have gone to volume production.
Expertise in low power design techniques.
Familiarity with UVM and Matlab.
Ability to write assertions and exposure to Formal verification.

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