Next-Gen High-Speed HBM LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $145,600–$218,400 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $198k

This role $182k

$134k $250k

below market most similar roles pay here above market

This role pays less than 61% of similar roles. Most pay $168,175–$227,300 — the blue band above. At the midpoint, this role pays about $182k versus about $198k for comparable roles.

Based on 240 similar postings.

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About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Next-Gen High-Speed HBM LPDDR Memory Controller ASIC Digital Design Engineer

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Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer The Senior ASIC Design Engineer joins the Next Generation, High-Speed, Memory and Cache Controller Design Team to develop high-speed HBM, LPDDR, and DDR memory controllers. This role involves architecture, RTL coding, and deployment of memory systems into products, specifically focusing on the front end interfacing with CPUs, GPUs, DSPs, and multimedia processors. Key responsibilities include developing architecture specifications, driving micro-architecture, implementing RTL, and performing debugging, synthesis, timing closure, physical design support, gate level simulations, and power analysis. Candidates must possess expertise in LPDDR memory, cache controllers, NoC based architectures, and x86 or ARM CPU/bus architectures. The work addresses the technical challenge of enabling high-speed 1Ghz+ designs while enforcing proper memory transaction ordering to conform to ISA architecture specifications.

Skills

ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture

What you'll do

Develop architecture and design specifications for next-generation high-speed memory systems.
Drive the micro-architecture for specific portions of the logic design.
Implement and deliver high-quality RTL code for memory controllers.
Debug designs and provide technical support when integrated into the rest of the chip.
Perform synthesis, timing closure, and physical design support.
Conduct gate level simulations and power analysis.
Contribute to improvements in design methodology to increase productivity and quality.

What we're looking for

Master's degree in Computer Engineering and/or Electrical Engineering.
4+ years of ASIC design, verification, validation, or integration experience with a Bachelor's degree.
3+ years of ASIC design, verification, validation, or integration experience with a Master's degree.
2+ years of ASIC design, verification, validation, or integration experience with a PhD.
5+ years of ASIC design, RTL coding, and front-end digital design experience.
3+ years of Hardware Architecture experience.
Experience with LPDDR memory, cache controllers, NoC based architectures, and HBM memory type designs (preferred).
Experience with x86 or ARM CPU/bus architectures and memory transaction ordering (preferred).

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