High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $140,000–$229,800 / yr
Posted: 8 days ago
Freshness: Confirmed live yesterday
Closes: Mar 2, 2027
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k

This role $185k

$129k most similar roles pay here $243k

This role pays less than 59% of similar roles. Most pay $174,250–$227,300 — the shaded band above. At the midpoint, this role pays about $185k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

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Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer will join the Next Generation, High-Speed, Memory and Cache Controller Design Team to develop high-speed memory systems for QCT products. This role involves working on architecture, RTL coding, and deployment of next-generation designs while driving micro-architecture for specific logic portions. The engineer is responsible for implementing and delivering RTL, collaborating with verification engineers to ensure high quality, and performing debugging across the chip. Key tasks include synthesis, timing closure, physical design support, gate level simulations, and power analysis. The role focuses on solving technical challenges in memory controllers interfacing with CPUs, GPUs, DSPs, and multimedia processors. Required expertise includes HBM, LPDDR, NoC-based architectures, SRAM, and L3 cache controller designs, alongside experience with x86 or ARM CPU/bus architectures to ensure proper transaction ordering for ISA specifications.

Skills

ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture

What you'll do

Develop architecture and design specifications for next-generation high-speed memory systems.
Implement RTL coding for high-speed HBM, LPDDR, and DDR memory controllers.
Drive the micro-architecture of specific logic design components.
Collaborate with verification engineers to deliver high-quality designs.
Debug designs and provide support during integration into the larger chip system.
Perform synthesis, timing closure, physical design support, and power analysis.
Contribute to improvements in design methodology to increase productivity and quality.

What we're looking for

Bachelor's degree in Science, Engineering, or a related field.
Master's degree in Computer Engineering and/or Electrical Engineering.
4+ years of experience in ASIC design, verification, validation, or integration with a Bachelor's degree.
3+ years of experience in ASIC design, verification, validation, or integration with a Master's degree.
2+ years of experience in ASIC design, verification, validation, or integration with a PhD.
5+ years of experience in ASIC design, RTL coding, and front-end digital design.
3+ years of Hardware Architecture experience.
Experience with high-speed digital design, LPDDR/HBM memory, and NoC based architectures.