below marketmost similar roles pay hereabove market
This role pays less than
58%
of similar roles. Most pay
$167,137–$223,000
— the blue band above.
At the midpoint, this role pays about
$182k
versus about
$195k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer
The hardware micro-architects and RTL designers on this team develop SOC Interconnects, Cache, and Memory Controllers for Snapdragon platforms across smartphones, PCs, Chromebooks, VR, AR, and automotive solutions. You will micro-architect, design, and validate RTL for blocks and modules of SOC Interconnects, Interconnect Caches, and memory subsystems. Daily responsibilities include identifying hardware optimizations for performance, power, and cost, evaluating complex algorithm feasibilities, developing specifications, and providing essential verification and debugging throughout project cycles. You will utilize Verilog, SystemVerilog, Synopsys synthesis, and C/C++/Python programming languages. The role requires expertise in Computer Architecture, Computer Arithmetic, and low power design to solve technical challenges in ASIC design, verification, and integration for high-speed memory subsystems and system-level power designs.
Micro-architect, design, and validate RTL for SOC interconnects, caches, and memory subsystems.
Develop micro-architecture specifications and RTL for new generation designs.
Identify hardware optimizations to improve performance, power efficiency, and silicon cost.
Evaluate the hardware feasibility of complex algorithms and technical requirements.
Perform verification and debugging activities throughout the entire project cycle.
Optimize clock speeds and minimize silicon costs for production designs.
Troubleshoot silicon issues for products relevant to the assigned design.
What we're looking for
Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field with 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field with 2+ years of ASIC design, verification, validation, integration, or related work experience.
Experience or course work in Verilog/SystemVerilog design, Synopsys synthesis, low power design, test plan development, and coverage-based design verification.
Experience or course work in Computer Architecture, Computer Arithmetic, low power design, and C/C++/Python programming languages (preferred).
Experience or course work in designing RTL for CPU and cache controller blocks in ASIC (preferred).
Prior experience in ASIC Design and DV (preferred).
Good communication skills and a desire to work as a team player.