Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $140,000–$210,000 / yr
Posted: 6 days ago
Closes: Dec 19, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $194k

This role $175k

$129k most similar roles pay here $238k

This role pays less than 71% of similar roles. Most pay $171,274–$216,250 — the shaded band above. At the midpoint, this role pays about $175k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 828 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 508 roles with salary data.

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At a glance

TL;DR · Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Role Posting Log in to save

The Memory Subsystem Performance Architect at Qualcomm Technologies will lead the performance modeling and optimization of high-bandwidth memory subsystems for next-generation SoCs, working closely with architecture, design, and software teams from concept to post-silicon validation. This role involves developing C++/SystemC models to analyze HBM-based systems, identifying bottlenecks across memory, interconnect, caches, and compute, and collaborating with cross-functional teams to influence design decisions. The ideal candidate has 3+ years of experience in performance modeling or system architecture, strong proficiency in C++, and knowledge of memory hierarchies and DRAM systems. Preferred qualifications include hands-on experience with HBM2/3 architectures, AI/ML SoCs, and post-silicon analysis, making this a critical role for advancing cutting-edge semiconductor technology.

Skills

C++ SystemC HBM Memory_Hierarchies DRAM_Systems AI/ML GPU HPC Post_Silicon_Performance_Analysis SoC_Architecture TLM HBM2 HBM2E HBM3

What you'll do

Develop and maintain C++ / SystemC performance models for HBM-based memory subsystems.
Define and execute experiments to evaluate HBM architecture features and system-level trade-offs.
Identify performance bottlenecks across HBM, interconnect, caches, and compute.
Influence design decisions by collaborating with cross-functional teams on SoCs.
Research industry trends and innovations in HBM and advanced packaging.

What we're looking for

3+ years of experience in performance modeling or memory/system architecture.
Proficient in C++ and experienced with SystemC/TLM modeling.
Solid understanding of memory hierarchies and DRAM systems.
Hands-on experience with HBM2/HBM2E/HBM3 architectures preferred.
Experience with AI/ML, GPU, or HPC-class SoCs beneficial.
Familiarity with post-silicon performance analysis and silicon correlation.
Ability to translate performance data into clear architectural recommendations.

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