Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

Confirmed live yesterday Low trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $140,000–$210,000 / yr
Posted: 43 days ago
Freshness: Confirmed live yesterday
Closes: Jan 26, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $195k

This role $175k

$129k most similar roles pay here $241k

This role pays less than 72% of similar roles. Most pay $172,000–$218,875 — the shaded band above. At the midpoint, this role pays about $175k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Role Posting Log in to save

Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer will join the ASICS Engineering team to develop SOC Interconnects, Cache and Memory Controllers for Snapdragon platforms across mobile, PC, and automotive devices. The role involves micro-architecting, designing, and validating RTL for memory subsystems while optimizing hardware design for performance, power, cost, and clock speed. Daily responsibilities include evaluating complex algorithm feasibility, developing specifications for new generation designs, performing verification and debugging throughout project cycles, and troubleshooting silicon issues. Candidates should possess skills in Verilog, SystemVerilog, Synopsys synthesis, low power design, and coverage-based verification. Preferred technical competencies include Computer Architecture, Computer Arithmetic, and proficiency in C, C++, or Python. The role focuses on solving critical hardware challenges within the memory subsystem domain to improve silicon efficiency for high-performance computing environments.

Skills

Verilog SystemVerilog ASIC Design RTL Synopsys Synthesis Low Power Design Computer Architecture C C++ Python Design Verification SOC Interconnects Memory Subsystems

What you'll do

Micro-architect, design, and validate RTL for SOC interconnects, cache modules, and memory subsystems.
Develop micro-architecture specifications for new generation hardware designs.
Implement RTL code based on defined micro-architectures for various SoC components.
Evaluate the hardware feasibility of complex algorithms and technical requirements.
Perform verification and debugging activities throughout the entire project cycle.
Optimize hardware designs to improve performance, power efficiency, and silicon cost.
Troubleshoot silicon issues in products relevant to your specific design area.

What we're looking for

Bachelor's degree in Science, Engineering, or a related field.
Master's degree in Science, Engineering, or a related field.
PhD in Science, Engineering, or a related field.
4+ years of experience in ASIC design, verification, validation, or integration with a Bachelor's degree.
3+ years of experience in ASIC design, verification, validation, or integration with a Master's degree.
2+ years of experience in ASIC design, verification, validation, or integration with a PhD.
Experience or coursework in Verilog/SystemVerilog design, Synopsys synthesis, low power design, and coverage-based design verification.
Proficiency in Computer Architecture, Computer Arithmetic, and C/C++/Python programming languages.

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