below marketmost similar roles pay hereabove market
This role pays less than
88%
of similar roles. Most pay
$176,450–$227,500
— the blue band above.
At the midpoint, this role pays about
$152k
versus about
$202k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
589 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 563 roles with salary data.
Next-Gen System Cache ASIC Digital Design Engineer joins the ASICS Engineering team to develop SOC Interconnects, Cache, and Memory Controllers for Snapdragon platforms. This role involves micro-architecting, designing, and validating RTL for blocks and modules within memory subsystems and power systems. You will evaluate hardware feasibility for complex algorithms, develop specifications for new generation designs, and perform essential verification and debugging throughout the project cycle. Key responsibilities include optimizing hardware for performance, power, and cost while troubleshooting silicon issues. The position requires proficiency in Verilog, SystemVerilog, Synopsys synthesis, and low power design. Candidates should possess skills in Computer Architecture, Computer Arithmetic, and programming in C/C++ or Python. The work focuses on solving hardware design challenges for smartphones, PCs, Chromebooks, virtual reality, and automotive solutions.
Micro-architect, design, and validate RTL for SOC interconnects, caches, and memory subsystems.
Develop micro-architecture specifications and RTL for new generation designs.
Identify hardware optimizations to improve performance, power efficiency, and silicon cost.
Evaluate the hardware feasibility of complex algorithms and technical requirements.
Perform essential verification and debugging activities throughout the entire project cycle.
Troubleshoot silicon issues for products relevant to the corresponding design.
Optimize clock speeds and silicon costs for high-performance products.
What we're looking for
Bachelor's degree in Science, Engineering, or related field with 2+ years of ASIC design, verification, validation, or integration experience.
Master's degree in Science, Engineering, or related field with 1+ year of ASIC design, verification, validation, or integration experience.
PhD in Science, Engineering, or related field.
Bachelor's, Master's, or PhD in Computer Engineering, Computer Science, or Electrical Engineering with a GPA greater than 3.5.
Experience or course work in Verilog/SystemVerilog design, Synopsys synthesis, low power design, test plan development, and coverage-based design verification.
Experience or course work in Computer Architecture, Computer Arithmetic, low power design, and C/C++/Python programming languages (preferred).
Experience or course work in designing RTL for CPU or cache controller blocks in ASIC (preferred).
Prior experience in ASIC Design and DV (preferred).