Analog/Mixed Signal ASIC Design Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$145,600–$218,400 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $208k
This role $182k
$134k $257k
below market most similar roles pay here above market

This role pays less than 62% of similar roles. Most pay $173,375–$241,750 — the blue band above. At the midpoint, this role pays about $182k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Analog/Mixed Signal ASIC Design Engineer

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The Analog/Mixed Signal ASIC Design Engineer joins the Mixed-Signal IP design team to develop high-performance, low-power mixed-signal IPs for SOCs and RF transceiver products. This role involves architecture definition, analog and digital design partitioning, and schematic design for components including SerDes, DDR, PLL, DAC, ADC, and sensors. Daily responsibilities include schematic capture and circuit simulations using the Cadence Virtuoso tool suite, collaborating with layout and digital teams on design implementation and verification, and supporting post-silicon bringup and production. Candidates must possess expertise in analog circuit design, utilizing tools such as Cadence, SPICE, MATLAB, and Verilog/VHDL. The work addresses technical challenges in advanced silicon process technologies for 5G, AI/ML, compute, and automotive applications, requiring a strong understanding of signals, systems, and sampled domain signal processing.

Skills

Cadence Virtuoso SPICE Python Matlab Verilog VHDL ASIC Design Mixed Signal Design Analog Circuit Design SerDes DDR PLL DAC ADC FinFET CMOS Signal Processing

What you'll do

  • Define architectures and perform analog/digital design partitioning for mixed-signal IPs.
  • Perform schematic capture and circuit simulations using the Cadence Virtuoso tool suite.
  • Execute design implementation and verification for IP delivery to SOC customers.
  • Coordinate with layout and digital teams to ensure successful IP integration.
  • Conduct post-silicon verification and debug during the product bringup phase.
  • Provide ongoing production support for mixed-signal integrated circuits.
  • Design high-performance, low-power IPs including SerDes, DDR, PLL, DAC, and ADC.

What we're looking for

  • Master's degree in Electrical Engineering or related field.
  • Bachelor's degree in Electrical Engineering with 2+ years of analog/mixed-signal IC design experience and 4+ years of ASIC design experience.
  • PhD in Electrical Engineering or related field with 2+ years of ASIC design experience.
  • Demonstrated interest in analog circuit design through coursework or work experience.
  • Experience using ASIC design tools such as Cadence Virtuoso.
  • 2+ years of experience using one or more design tools like CADENCE, SPICE, MATLAB, or Verilog/VHDL.
  • Several years of industry experience in analog integrated circuit or system design (preferred).
  • Experience as an analog designer of mixed-signal IPs like SerDes, DDR, PLL, DAC, or ADC (preferred).

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