This role pays less than
60%
of similar roles. Most pay
$174,250–$217,500
— the shaded band above.
At the midpoint, this role pays about
$178k
versus about
$196k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
623 open roles
on FindRole.
Listed pay typically runs
$148,300–$222,500
across 603 roles with salary data.
The Analog/Mixed Signal ASIC Design Engineer joins the Mixed-Signal IP design team to develop high-performance, low-power mixed-signal IPs including SerDes, DDR, PLL, DAC, ADC, and sensors in advanced silicon process technologies. Working within a multidisciplinary team of architects and designers, you will perform architecture definition, analog and digital design partitioning, schematic capture, and circuit simulations using the Cadence Virtuoso tool suite. You will collaborate with cross-functional layout and digital teams for implementation and verification while supporting product test teams with post-silicon verification, bringup, and production support. The role requires expertise in analog integrated circuit design, potentially utilizing Matlab, Python, and Verilog/VHDL. This position focuses on solving complex integration challenges for SOCs and RF transceiver products targeted at 5G, AI/ML, compute, and automotive applications within nanometer planar CMOS or FinFET technologies.
Define architecture and perform analog/digital design partitioning for mixed-signal IPs.
Create schematic designs for high-performance and low-power components like SerDes, DDR, PLL, DAC, and ADC.
Perform circuit simulations using the Cadence Virtuoso tool suite.
Execute design implementation and verification in coordination with layout and digital teams.
Deliver completed mixed-signal IPs to SoC customers.
Conduct post-silicon verification, bringup, and debugging for product test teams.
Provide technical support for production and manufacturing challenges.
What we're looking for
A Bachelor's degree in Electrical Engineering with 2+ years of experience in analog or mixed-signal IC design and 4+ years of ASIC design/verification experience.
A Master's degree in Electrical Engineering or a related field with 4+ years of ASIC design, verification, or related work experience.
A PhD in Electrical Engineering or a related field with 2+ years of ASIC design, verification, or related work experience.
Experience using at least one design tool such as Cadence Virtuoso, SPICE, MATLAB, Verilog, or VHDL.
Demonstrated interest in analog circuit design through relevant coursework or professional experience.
Experience designing mixed-signal IPs like SerDes, DDR, PLL, DAC, ADC, or sensors.
Proficiency with Matlab and Python for mixed-signal architecture and system integration.
Understanding of signals and systems, sampled domain signal processing, and design for yield/production challenges.