ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$145,600–$218,400 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $196k
This role $182k
$135k $249k
below market most similar roles pay here above market

This role pays less than 58% of similar roles. Most pay $168,500–$223,000 — the blue band above. At the midpoint, this role pays about $182k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · ASIC/RTL Design Engineer for High-speed Interfaces

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The ASIC/RTL Design Engineer for High-speed Interfaces joins the Mixed-Signal IP team to develop next-generation, high-performance, low-power interface IPs. You will architect, design, and implement complex mixed-signal IP blocks, including SerDes, DDR, and die-to-die interconnects for mobile, compute, data center, and AI products. Daily responsibilities involve developing micro-architecture and RTL, performing lint checking, clock domain crossing analysis, synthesis, formal verification, and static timing analysis. You will also design DFT logic, create hardware specifications, and collaborate with verification and physical design teams on floorplanning and timing closure. Required skills include proficiency with VCS, Fusion Compiler, PrimeTime, Power Compiler, and Spyglass. You must possess expertise in computer architecture, digital signal processing, and low-power design techniques to solve complex semiconductor integration challenges.

Skills

ASIC Design RTL Micro-architecture SerDes DDR Mixed-Signal IP VCS Fusion Compiler PrimeTime Power Compiler Spyglass DFT Static Timing Analysis Formal Verification Python Perl Digital Signal Processing PCIe USB UFS MIPI

What you'll do

  • Architect and define the digital design of high-speed interface IPs like SerDes, DDR, and die-to-die interconnects.
  • Develop micro-architecture and implement RTL for complex mixed-signal IP blocks.
  • Apply advanced techniques in computer architecture and digital signal processing to optimize power, performance, and area.
  • Perform lint checking, clock domain crossing analysis, synthesis, formal verification, and static timing analysis.
  • Design and analyze DFT logic, including ATPG for stuck-at fault and transition delay fault coverage.
  • Create comprehensive hardware specifications and design documentation.
  • Define test plans and fix bugs in coordination with the design verification team.
  • Support SoC integration, pre-silicon simulation, and post-silicon bring-up.

What we're looking for

  • Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 7+ years of experience in RTL and ASIC design.
  • 5+ years of hands-on experience in micro-architecture and digital design for mixed-signal IPs such as SerDes, DDR PHY, PLLs, DACs, ADCs, and sensors.
  • Proficiency with industry-standard front-end ASIC design tools including VCS, Fusion Compiler, PrimeTime, Power Compiler, and Spyglass.
  • Ph.D. in Electrical Engineering with 5+ years of industry experience in high-speed digital circuit design (preferred).
  • Strong background in low-power digital design techniques (preferred).
  • Expertise in computer architecture, digital signal processing, and algorithm development (preferred).
  • Experience developing automation scripts and design productivity tools using Python or Perl (preferred).

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