ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Closes
Mar 7, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k
This role $175k
$129k most similar roles pay here $241k

This role pays less than 74% of similar roles. Most pay $175,000–$216,562 — the shaded band above. At the midpoint, this role pays about $175k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · ASIC/RTL Design Engineer for High-speed Interfaces

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The ASIC/RTL Design Engineer for High-speed Interfaces joins the Mixed-Signal IP team to develop next-generation, high-performance, and low-power interface IPs including SerDes, DDR, and die-to-die interconnects. Working within a cross-functional environment, you will architect, design, implement, and validate complex mixed-signal IP blocks while managing the full ASIC design flow from RTL through GDSII. Daily responsibilities include developing micro-architecture, implementing RTL, performing lint checking, clock domain crossing analysis, and designing DFT logic for stuck-at fault and transition delay fault coverage. You will utilize industry-standard tools such as VCS, Fusion Compiler, PrimeTime, Power Compiler, and Spyglass. The role requires expertise in computer architecture, digital signal processing, and low-power design techniques to solve critical challenges in advanced semiconductor technologies across mobile, compute, data center, and AI product portfolios.

Skills

RTL ASIC Design SerDes DDR PCIe USB UFS MIPI VCS Fusion Compiler PrimeTime Power Compiler Spyglass Python Perl DFT STA CDC GDSII

What you'll do

  • Architect and define the digital design of high-speed interface IPs such as SerDes, DDR, and die-to-die interconnects.
  • Develop micro-architecture and implement RTL for complex mixed-signal IP blocks.
  • Apply advanced techniques in computer architecture and signal processing to optimize power, performance, and area (PPA).
  • Perform lint checking, clock domain crossing analysis, synthesis, formal verification, and static timing analysis using industry tools.
  • Design and analyze DFT logic including ATPG for stuck-at fault and transition delay fault coverage.
  • Create comprehensive hardware specifications and design documentation.
  • Collaborate with verification teams to define test plans, verify designs, and resolve bugs.
  • Support physical design tasks such as floorplanning, placement, and timing closure while assisting in SoC integration and debug.

What we're looking for

  • Bachelor's degree in Science or Engineering with 4+ years of experience, Master's with 3+ years, or PhD with 2+ years of relevant experience.
  • Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 7+ years of experience in RTL and ASIC design.
  • 5+ years of hands-on experience in micro-architecture and digital design for mixed-signal IPs like SerDes, DDR PHY, PLLs, DACs, ADCs, and sensors.
  • Proficiency with industry-standard front-end ASIC design tools including VCS, Fusion Compiler, PrimeTime, Power Compiler, DFT Compiler, and Spyglass.
  • Ph.D. in Electrical Engineering with 5+ years of experience in high-speed digital circuit design (preferred).
  • Strong background in low-power digital design techniques (preferred).
  • Expertise in computer architecture, digital signal processing, algorithm development, or automation scripting using Python or Perl (preferred).

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