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RTL ASIC Design SerDes DDR PCIe USB UFS MIPI VCS Fusion Compiler PrimeTime Power Compiler Spyglass Python Perl DFT STA CDC GDSII +14 more Show less

ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture +11 more Show less

SystemVerilog UVM Verilog VHDL Python C++ Perl Formal Verification UPF AMBA AXI AHB APB RTL Object-Oriented Programming Scripting Automation +12 more Show less

ASIC RTL Design Verilog System Verilog VHDL Python Perl SoC Logic Design System Simulation Clock Design +6 more Show less

CMOS Mixed Signal Design Cadence ADE MATLAB SPICE Verilog VHDL PLL SERDES 5G Analog Design Automation Layout Silicon Evaluation +8 more Show less

ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture +11 more Show less

Electrical Engineering Computer Engineering Computer Science Risk Analysis Product Design Rules Manufacturing Process Setup Technical Risk Assessment Empirical Evaluation New Product Bring-up Documentation +5 more Show less

ASIC SoC RTL Design Static Timing Analysis Synthesis Verification Silicon Bring-up Python Tcl Perl FPGA Low-power Design IP Integration System Simulation Automation +10 more Show less

ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture +11 more Show less

Digital Design FPGA Silicon Bring-up Characterization Debug Mixed Signal Design MIPI HDMI TCON Micro-architecture Emulation Verification +7 more Show less

Cadence Virtuoso ASIC Design SerDes DDR PLL DAC ADC Python MATLAB SPICE Verilog VHDL Circuit Simulation Schematic Capture FinFET CMOS +11 more Show less

SystemVerilog UVM Verilog VHDL Python C++ Perl Formal Verification UPF AMBA AXI AHB APB RTL Object-Oriented Programming Scripting Automation +12 more Show less

Verilog SystemVerilog ASIC Design RTL Synopsys Synthesis Low Power Design Computer Architecture C C++ Python Design Verification SOC Interconnects Memory Subsystems +8 more Show less

DTCO STA Hspice Finesim PrimeSim AFS Spectre PT Tempus Genus Innovus Python Perl TCL Unix Shell C/C++ RTL to GDS PPA Analysis +13 more Show less

RTL ASIC Design Mixed-Signal IP Digital Signal Processing VCS Fusion Compiler PrimeTime Power Compiler Spyglass DFT STA CDC Python Perl GDSII Synthesis Formal Verification Floorplanning Pre-silicon Simulation +14 more Show less

UVM SystemVerilog Verilog SystemC Matlab C DPI-C Formal Verification RTL ASIC Digital Verification Scripting CMOS +8 more Show less

ASIC Design RTL UVM System C DPI-C Matlab Formal Verification DFT Low Power Design CMOS Digital Design Verification Test Bench +7 more Show less

ASIC RTL DSP MATLAB UVM System C DPI-C Digital Logic Design CMOS Micro-architecture Bus Fabrics Communication Systems +7 more Show less

UVM C++ C Matlab Formal Verification System C DPI-C RTL FPGA Emulation Scripting ASIC Design Digital Verification CMOS +9 more Show less

UVM C++ C System C DPI-C Formal Verification Matlab RTL FPGA Emulation Digital Verification ASIC Scripting CMOS +9 more Show less