Hardware ASIC Packaging SI/PI Simulation and Design Lead

Cisco

Confirmed live today High trust
Remote

Quick summary

Work type
Remote
Location
San Jose, CAHouston, TXSan Francisco, CADenver, COBoston, MAAllentown, PADallas, TXAtlanta, GABoise, IDCary, NCSan Diego, CA
Salary
$186,900–$267,700 / yr
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live today
Closes
Dec 31, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $210k
This role $227k
$153k $280k
below market most similar roles pay here above market

This role pays more than 65% of similar roles. Most pay $177,300–$243,600 — the blue band above. At the midpoint, this role pays about $227k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · Hardware ASIC Packaging SI/PI Simulation and Design Lead

Role Posting Log in to save

The Hardware ASIC Packaging SI/PI Simulation and Design Lead joins the Cisco Silicon One team to develop next-generation ASIC packaging for high-performance silicon devices. This role involves defining, designing, and verifying packaging for various platforms, specifically focusing on ultra-high-speed signaling, power, performance, and area goals. Key responsibilities include implementing design rules, analyzing substrate signal and power integrity across interposers and PCBs, and performing post-layout extraction. The candidate will utilize industry-standard EDA tools including Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, and SPICE for circuit-level analysis. Technical expertise must cover Transmission Line Theory, electromagnetics, and 56G PAM4 SerDes architectures. The work addresses complex technical issues in 2.5D fanout technologies, high-bandwidth memory interfaces, and die-to-die interconnects like UCIe or proprietary designs.

Skills

ASIC Signal Integrity Power Integrity Cadence Sigrity Ansys HFSS Keysight ADS SPICE Cadence APD Ansys EM PAM4 SerDes 2.5D Fanout HBM UCIe IBIS Vector Network Analysis Transmission Line Theory Electromagnetics PCB. Design Mixed-Signal Circuit Design

What you'll do

  • Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
  • Analyze substrate signal integrity (SI) and power integrity (PI) to provide feedback for interposer, substrate, and PCB layouts.
  • Design and document ASIC packages for high-volume release, including post-layout extraction and reporting.
  • Define processes, methods, and tools for the design and implementation of complex ASIC and package developments.
  • Lead chip architecture discussions and review intricate IC and analog/mixed-signal circuit designs.
  • Mentor the signal integrity team and junior engineers to ensure technical specifications and innovative solutions are met.
  • Conduct detailed layout reviews and physical design validation using EDA tools to ensure signal performance and crosstalk mitigation.

What we're looking for

  • Must have a Bachelor's in Electrical Engineering with 8+ years of signal and power integrity experience.
  • Must have a Master's in Electrical Engineering with 6+ years of signal and power integrity experience.
  • Must have a PhD in Electrical Engineering with 3+ years of signal and power integrity experience.
  • Must have experience with high-speed design principles including Transmission Line Theory, electromagnetics, and 56G PAM4 SerDes architectures.
  • Must have experience with pre- and post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, or Keysight ADS.
  • Must have experience conducting layout reviews and physical design validation using Cadence APD or Ansys EM flows.
  • Must have experience with SPICE for circuit-level analysis and signal modeling.
  • Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity.

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