Signal & Power Integrity Hardware ASIC Simulation Engineer

What you'll do

• Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
• Analyze substrate signal integrity (SI) and power integrity (PI) across interposer, substrate, and PCB levels.
• Provide technical feedback to the layout team to develop optimal solutions for high-performance ASIC packaging.
• Perform post-layout extraction and reporting to ensure high-volume, high-quality production of ASIC packages.
• Conduct detailed layout reviews and physical design validation using industry-standard EDA tools like Cadence Sigrity and Ansys HFSS.
• Resolve complex technical issues by collaborating with system partners, vendors, and design leads.
• Perform circuit-level analysis and signal modeling using SPICE for performance validation.

What we're looking for

• Bachelor's degree in Electrical Engineering with 6+ years of experience, Master's with 3+ years, or PhD with 0+ years required.
• Expertise in high-speed design principles including Transmission Line Theory, electromagnetics, and 56G PAM4 SerDes architectures.
• Proficiency in pre- and post-layout SI/PI simulations using tools like Cadence Sigrity, Ansys HFSS, or Keysight ADS.
• Experience conducting layout reviews and physical design validation using Cadence APD or Ansys EM flows.
• Working knowledge of SPICE for circuit-level analysis and signal modeling.
• Ability to articulate technical concepts clearly to diverse audiences in both verbal and written formats (preferred).
• Experience with high-bandwidth memory, die-to-die interfaces, or advanced packaging like CoWoS and EMIB (preferred).
• Working knowledge of Vector Network Analysis and basic knowledge of IBIS (preferred).