ASIC DTCO, Timing and Technology Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$145,600–$218,400 / yr
Posted
40 days ago
Freshness
Confirmed live yesterday
Closes
Mar 16, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $182k
$135k $240k
below market most similar roles pay here above market

This role pays less than 59% of similar roles. Most pay $175,450–$227,300 — the blue band above. At the midpoint, this role pays about $182k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · ASIC DTCO, Timing and Technology Engineer

Role Posting Log in to save

The ASIC DTCO, Timing and Technology Engineer joins the ASICS Engineering group to perform DTCO analysis for Mobile, Compute, Automotive, and IOT markets. This role involves evaluating process technology entitlement for SOC products at the block, IP, and system levels using advanced 5nm, 4nm, and 2nm technologies. Key responsibilities include performing Spice simulations using Hspice, Finesim, PrimeSim, AFS, and Spectre for power and performance validation, alongside STA sign off using PT/PT-SI and Tempus. The engineer will execute block level PPA analysis from RTL to GDS flow for hard macros using FC Synthesis, FC Place and Route, Genus, and Innovus. Required skills include Python, Perl, TCL, Unix shell, and C/C++. The role focuses on driving Fmax optimization, PPAY, and cost improvements across various production technologies.

Skills

ASIC Design DTCO STA Hspice Finesim PrimeSim AFS Spectre PT-SI Tempus Genus Innovus Python Perl TCL Unix Shell C/C++ ML Modeling RTL to GDS PPA Analysis

What you'll do

  • Evaluate process technology entitlement (PPAY) for SoC products at the block and system levels.
  • Perform Spice simulations using Hspice, Finesim, PrimeSim, AFS, or Spectre for power and performance validation.
  • Execute STA sign-off using PT/PT-SI and Tempus tools.
  • Conduct block-level PPA analysis and implementation from RTL to GDS using FC Synthesis, Place and Route, Genus, and Innovus.
  • Drive Fmax optimization, PPAY, and cost reduction improvements for multiple blocks.
  • Support new advanced process technology bring-up from PDK to VLSI design.
  • Develop scripts and tools using Python, Perl, TCL, Unix shell, and C/C++.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
  • Experience performing Spice simulations using Hspice, Finesim, PrimeSim, AFS, or Spectre for power and performance validation.
  • Experience with STA sign off using PT/PT-SI and Tempus.
  • Experience with block level PPA analysis and implementation using FC Synthesis, FC Place and Route, Genus, and Innovus.
  • Proficiency in programming languages including Python, Perl, TCL, Unix shell, and C/C++.
  • ML modeling experience (preferred).

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