ASIC DTCO Timing and Technology Engineer

Qualcomm

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
45 days ago
Freshness
Confirmed live 2 days ago
Closes
Jan 24, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k
This role $175k
$129k most similar roles pay here $239k

This role pays less than 71% of similar roles. Most pay $170,000–$223,000 — the shaded band above. At the midpoint, this role pays about $175k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · ASIC DTCO Timing and Technology Engineer

As an ASIC DTCO, Timing and Technology Engineer within the ASICS Engineering group, you will perform critical DTCO analysis for products targeting the Mobile, Compute, Automotive, and IOT markets. You will evaluate process technology entitlement for SOC products at both block and system levels using advanced 5nm, 4nm, and 2nm technologies. Your daily responsibilities include performing Spice simulations for power and performance validation, conducting STA sign-off, and executing block level PPA analysis from RTL to GDS flow. You will collaborate with foundry teams and EDA partners to drive Fmax optimization and cost improvements. The role requires proficiency in tools like Hspice, PrimeSim, Tempus, Genus, and Innovus, alongside programming skills in Python, Perl, TCL, Unix shell, and C/C++. Experience with ML modeling is considered a plus for this technical position.

What you'll do

  • Perform DTCO analysis for SoC products across mobile, compute, automotive, and IoT markets.
  • Evaluate process technology entitlement (PPAY) at the block/IP level and system level for advanced nodes.
  • Conduct Spice simulations using Hspice, Finesim, PrimeSim, AFS, or Spectre for power and performance validation.
  • Perform STA sign-off using PT/PT-SI and Tempus tools.
  • Execute block-level PPA analysis and implementation from RTL to GDS flow using synthesis and place and route tools.
  • Drive Fmax optimization, PPAY, and cost reductions in collaboration with foundry, EDA, CAD, and IP teams.
  • Improve design convergence processes and support new advanced process technology bring-up from PDK to VLSI design.
  • Develop scripts and automation using Python, Perl, TCL, Unix shell, or C/C++.

What we're looking for

  • Bachelor's degree with 4+ years of experience in ASIC design, verification, validation, or integration.
  • Master's degree with 3+ years of experience in ASIC design, verification, validation, or integration.
  • PhD with 2+ years of experience in ASIC design, verification, validation, or integration.
  • Experience performing Spice simulations for power and performance validation using Hspice, Finesim, PrimeSim, AFS, or Spectre.
  • Proficiency in STA sign off using PT/PT-SI and Tempus tools.
  • Experience with RTL to GDS flow including FC Synthesis, FC Place and Route, Genus, and Innovus.
  • Proficiency in programming languages including Python, Perl, TCL, Unix shell, and C/C++.
  • Machine learning modeling experience is preferred.

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