Digital ASIC Architect

Apple Inc

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Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$175,000–$308,500 / yr
Posted
2 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $214k
This role $242k
$148k $326k
below market most similar roles pay here above market

This role pays more than 72% of similar roles. Most pay $177,250–$250,000 — the blue band above. At the midpoint, this role pays about $242k versus about $214k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3595 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2772 roles with salary data.

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At a glance

TL;DR · Digital ASIC Architect

The Digital ASIC Architect joins the Motion Sensing Hardware team to define the digital architecture for next-generation motion-aware experiences. This role involves owning the digital architecture of motion sensing ASICs from concept through silicon, focusing on cost and power optimization. You will build high-level models, author detailed specifications, and define hardware/firmware partitioning, memory hierarchy, and bus topologies. Key responsibilities include developing sensing algorithms and signal processing pipelines while performing trade-off analyses for processors, DSP cores, and custom control engines. You will utilize MATLAB, Python, SystemC, and C/C++ to predict performance and co-simulate digital systems with behavioral analog front-ends. The work addresses technical challenges in spatial computing, gesture input, and head-tracked audio by designing ASICs for IMUs, magnetometers, and pressure sensors.

What you'll do

  • Define the digital architecture for motion sensing ASICs from concept through silicon.
  • Evaluate and down-select processors, DSPs, memory, and interface IP based on performance, power, and area.
  • Define hardware/firmware partitioning, memory hierarchy, bus topology, and clock/power domain structures.
  • Develop sensing algorithms and signal processing pipelines using MATLAB, Python, or SystemC.
  • Co-simulate digital designs with behavioral analog front-ends and MEMS models to validate system interactions.
  • Author detailed IP-level and IC-level specifications for processors, memory, and custom control engines.
  • Drive defect root cause analysis and resolution from initial bring-up through mass production.
  • Document architectural assumptions, risks, and waiver justifications for tape-out readiness sign-off.

What we're looking for

  • BS in Electrical Engineering or related field.
  • Minimum of 10 years of relevant industry experience.
  • Excellent written and verbal communication skills.
  • Deep expertise in digital ASIC architecture for sensor or mixed-signal systems (preferred).
  • Proven track record of defining and taping out high-volume, complex digital and mixed-signal ICs (preferred).
  • Strong foundation in system-level design, requirements development, and hardware/firmware partitioning (preferred).
  • Experience developing sensing algorithms and signal processing pipelines with modeling skills (preferred).
  • Experience with IC bring-up, silicon characterization, and system-level debug (preferred).

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