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Physical Design Synthesis PnR STA CTS Floorplanning Routing UPF Python Tcl Innovus ICC2 Fusion Compiler Genus PrimeTime Tempus LEC VLSI +13 more Show less

ASIC Physical Design Synthesis STA P&R Floor Planning Timing Closure IR Drop Analysis DFT UPF CMOS Mixed signal AI Flow RTL +9 more Show less

ASIC Physical Design Floorplanning Power Planning Clock Tree Synthesis Static Timing Analysis Signal Integrity RC Extraction DFT UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime +14 more Show less

ASIC Physical Design Logic Synthesis Formal Verification Equivalence Checking RTL Timing Closure Clock Domain Crossing MTBF Analysis Synopsys Cadence Python TCL Perl Make EDA Tools Netlisting ECO Generation +12 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture +9 more Show less

ASIC Physical Design Floor Planning Synthesis Verilog TCL Perl Python Shell GPU Architecture Timing Constraints Netlist +7 more Show less

Physical Design Cadence Innovus Tcl Python Place-and-Route Timing Analysis Physical Verification Digital Design Automation Micro-architecture Logic Design +6 more Show less

C++ VLSI Physical Design EDA Tools Machine Learning Graph Neural Networks Python Tcl Perl multithreading Distributed Computing ICC2 Innovus PrimeTime Tempus StarRC +10 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Scripting Verification Validation SoC IC Package +6 more Show less

C++ VLSI Physical Design Machine Learning Graph Neural Networks Python Tcl Perl ICC2 Innovus PrimeTime Tempus StarRC Multithreading Distributed Computing Parallel Computing EDA Tools +12 more Show less

Physical Design Static Timing Analysis Logic Synthesis Floorplanning Clock-tree Synthesis Routing ECO RTL Python Tcl Perl Make AI Deep Learning LLMs EDA Tools +11 more Show less

STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting EDA Tools VLSI ECO CMOS Digital Logic Design +11 more Show less

STA Timing Closure Physical Design TCL Python Perl Shell Scripting EDA Tools DFT Synthesis ECO Tapeout RTL Clocking OCV +10 more Show less

STA Timing Closure TCL Python Perl Shell Scripting EDA Tools DFT RTL Synthesis ECO PPA post silicon debug Tapeout OCV Cross-talk Clocking +12 more Show less

Physical Design TCL Python ASIC Integration Floorplanning Power Distribution Tapeout Voltage Drop Analysis Layout Verification DRC CAD Scripting +7 more Show less

STA PrimeTime Tempus ICC2 Innovus TCL Python Perl RTL GDS Spice Signal Integrity Layout Parasitic Extraction Timing Closure CTS POCV AOCV +12 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Validation Scripting SoC +5 more Show less

Physical Design SPICE RTL Standard Cell Optimization PLL Circuit Design Verification Jitter Measurement Hardware Engineering +4 more Show less

C++ VLSI Physical Design Computational Geometry Graph Theory Machine Learning ICC2 Innovus Multithreading Distributed Computing Algorithm Development C++17 C++14 +7 more Show less

ASIC SOC Physical Design RTL2GDSII Static Timing Analysis STA Floorplanning Place and Route DFT Scan MBIST LBIST FinFET CMOS Python TCL Perl Bash Makefile EDA Tools +15 more Show less