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Innovus Tempus Primetime Redhawk Voltus Calibre Pegasus Python Static Timing Analysis Hierarchical Design Timing Closure Power Integrity Analysis Custom Clock Design H-Tree Mesh Floor Planning Power Grid Planning Partitioning Pin Assignment +14 more Show less

RTL2GDSII EDA tools CMOS digital design principles Standard cells DFT Scan MBIST LBIST Physical design flows +4 more Show less

EDA tools CMOS digital design principles Standard cells DFT Scan MBIST LBIST Physical design flows +3 more Show less

C++ VLSI Python Perl Tcl ICC2 Innovus PrimeTime Tempus StarRC Reinforcement Learning GNNs Graph Neural Networks CI/CD +9 more Show less

C++ Python ICCAD tools Innovus Computational geometry Graph theory Algorithm development Multithreading Distributed computing High performance software design GUI development Machine learning VLSI Physical Design +8 more Show less

SPICE Python Kubernetes Terraform Docker CI/CD Prometheus Grafana PostgreSQL Git VLSI RTL Physical_Design Clocking_Solutions HDL Verilog SystemVerilog Cadence Synopsys Calibre +15 more Show less

C++ Python Perl Tcl ICC2 Innovus PrimeTime Tempus StarRC VLSI EDA Multithreading Distributed computing Reinforcement learning GNNs Graph Neural Networks CI/CD +12 more Show less

Tcl Python Cadence_Innovus Place-and-route Physical_Design Timing_Analysis Physical_Verification EDA Automation CI/CD +5 more Show less

Perl TCL Make Python Synopsys Cadence Logic Synthesis Equivalence Checking Formal Verification Clock Domain Crossing Checks MTBF Analysis RTL Design EDA Tools AI Utilization +9 more Show less

C C++ Python Perl Verilog VHDL UVM SystemC DVFlow CI/CD Linux +6 more Show less

Python TCL Perl shell scripting EDA tools APIs hierarchical design top-down design budgeting timing physical convergence multi-voltage power gated power retention Synthesis DFT insertion Floorplanning Clock and Power distribution Place and Route STA +14 more Show less

TCL Perl Python Synthesis DFT Floorplanning Clock_and_Power_Distribution Place_and_Route Timing_Electrical_Physical_Signoff Multi_Voltage_Design Power_Gating Hierarchical_Design Top_down_Design_Budgeting IP_Integration CAD_Tools Floorplanning_Tools P&R_Flows Static_Timing_Analysis Physical_Design_Verification_Flows Design_for_Yield Thermal_Management +16 more Show less

Python Tcl Spice Static Timing Analysis CAD Machine Learning Data Science Silicon Verification Power Delivery Analysis Parasitic Extraction Inductance Effects Physical Design Methodology SoC Designs Advanced Technology Nodes Interconnects Performance Analysis +10 more Show less

Python Tcl Spice static timing analysis tools inductance effects parasitic extraction performance analysis power delivery machine learning data science CAD tools Silicon verification methodologies advanced technology nodes SoC design经验 电气工程知识 计算机科学知识 +11 more Show less

Synopsys_Fusion_Compiler Synopsys_ICC2 Cadence_Genus Cadence_Innovus Python Perl TCL Shell_Scripting Timing_Analysis Physical_Design Clock_Tree_Synthesis Power_Optimization Logic_Optimization ASIC_Physical_Design CI/CD +10 more Show less