ASIC Physical Design Engineer

Cisco

Confirmed live today High trust
Closes in 3 days

Quick summary

Work type
On-site
Location
San Jose, CAAustin, TXRTP, NC
Employment
Full-time
Posted
19 days ago
Freshness
Confirmed live today
Closes
Oct 30, 2026 (soon)
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $193k
$141k $242k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $168,200–$218,000.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · ASIC Physical Design Engineer

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The ASIC Physical Design Engineer joins the Common Hardware Group to support the development of silicon, optics, and hardware platforms for switching, routing, and wireless products. This role focuses on the RTL-to-GDSII implementation for the Cisco Silicon One architecture. Key responsibilities include hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks to optimize performance and die size. The engineer will analyze tool flows, guide clock tree synthesis strategies, and execute timing ECO implementations. Required technical skills include experience with 7nm, 5nm, and 3nm process technologies using EDA tools such as Innovus, Tempus, Primetime, Redhawk, Voltus, or Calibre. Candidates should also possess competencies in Python, TCL, or Perl programming to support automation and design methodology enhancements.

Skills

RTL-to-GDSII Physical Design Static Timing Analysis STA Innovus Tempus Primetime Redhawk Voltus Calibre Python TCL Perl Clock Tree Synthesis CTS Power Integrity Floorplanning Place and Route Equivalence Checks

What you'll do

  • Execute RTL-to-GDSII implementation including floorplanning, place and route, and static timing analysis.
  • Optimize design performance and die size through power integrity and equivalence checks.
  • Analyze existing tool flows to identify and implement efficiency enhancements.
  • Guide clock tree synthesis strategies and provide actionable feedback to implementation teams.
  • Execute STA setup, convergence methodologies, and sign-off processes across multi-mode scenarios.
  • Complete Timing ECO implementation using Tweaker and Primetime-based flows.
  • Evaluate various timing methodologies and tools across different technologies and design types.

What we're looking for

  • Bachelor’s Degree in Electrical Engineering with 6+ years of Physical Design experience.
  • Master’s Degree in Electrical Engineering with 4+ years of Physical Design experience.
  • PhD in Electrical Engineering with 2+ years of Physical Design experience.
  • Experience with RTL2GDSII flow and design tapeouts in 7nm, 5nm, 3nm, or below process technologies.
  • Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre.
  • Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis (preferred).
  • Experience with static timing analysis, defining timing constraints, exceptions, corners, and voltage definitions (preferred).
  • Experience with Python, TCL, or Perl programming (preferred).

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