below marketmost similar roles pay hereabove market
This role pays less than
58%
of similar roles. Most pay
$171,375–$216,250
— the blue band above.
At the midpoint, this role pays about
$177k
versus about
$194k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
1623 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 1110 roles with salary data.
The Senior Physical Design and Timing Engineer will join a dynamic team to drive the physical design and timing of high-frequency, low-power CPUs, GPUs, LPUs, and SoCs. The role involves managing frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, power convergence, and ECO implementation at block, cluster, and full-chip levels. Candidates must possess hands-on experience in logic synthesis, placement, clock-tree synthesis, routing, and physical optimization. Required skills include Static Timing Analysis, timing-constraint development, and multi-mode, multi-corner timing closure factoring in IR drop and Xtalk. Proficiency in industry-standard EDA tools and scripting languages like Python, Tcl, Perl, and Make is required. The work focuses on improving power, performance, and area for complex high-performance computing hardware.
Drive physical design and timing for high-frequency and low-power CPUs, GPUs, LPUs, and SoCs.
Manage frontend and backend implementation from RTL to gds2, including synthesis and equivalence checking.
Execute floor-planning, timing constraints, and timing and power convergence.
Perform ECO implementation and physical optimization for complex blocks and full chips.
Conduct Static Timing Analysis and timing-constraint development for multi-mode and multi-corner designs.
Improve power, performance, and area through critical-path planning and methodology improvements.
Develop scalable optimization and signoff solutions using automation or AI/Agentic frameworks.
Utilize industry-standard EDA tools and scripting languages like Python, Tcl, and Perl.
What we're looking for
BS in Electrical or Computer Engineering with 5+ years of experience, or MS with 3+ years of experience in physical design, synthesis, and timing.
Hands-on experience taking complex blocks, IPs, or chips from RTL/netlist to tapeout through synthesis, floorplanning, placement, CTS, routing, and ECOs.
Demonstrated success improving power, performance, and area through design improvements, critical-path planning, or methodology/workflow improvements.
Hands-on experience in block, sub-chip, and full-chip level Static Timing Analysis and timing-constraint development.
Experience in multi-mode, multi-corner timing closure factoring in process variations, IR drop, and Xtalk.
Expertise and in-depth knowledge of industry-standard EDA tools.
Proficiency in Python, Tcl, Perl, Make, or similar scripting languages as well as AI/ML/DL/LLMs.
Physical design experience on high-performance CPUs, GPUs, LPUs, or AI accelerator designs (preferred).
Physical Design
Static Timing Analysis
STA
Power Analysis
Logic Synthesis
Equivalence Checking
Placement
Routing
Python
Perl
Tcl
Make
Cadence
Synopsys
Siemens
AI
ML
RTL
GDSII