Senior Physical Design and Timing Engineer

Nvidia

Confirmed live yesterday Trusted

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TXHillsboro, ORDurham, NC
Salary: $136,000–$218,500 / yr
Posted: 53 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k

This role $177k

$126k most similar roles pay here $229k

This role pays less than 52% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior Physical Design and Timing Engineer

Role Posting Log in to save

As a Senior Physical Design and Timing Engineer, you will join a dynamic team to drive the physical design and timing of high-frequency, low-power CPUs, GPUs, LPUs, and SoCs at block, cluster, and full chip levels. You will manage frontend and backend implementation from RTL to gds2, including synthesis, floor-planning, timing constraints, power convergence, and ECO implementation. The role requires hands-on experience in logic synthesis, placement, clock-tree synthesis, routing, and physical optimization. You must perform Static Timing Analysis and multi-mode, multi-corner timing closure while accounting for IR drop and Xtalk. Required skills include proficiency in industry-standard EDA tools and scripting languages like Python, Tcl, Perl, or Make. Additionally, the role involves leveraging AI/ML/DL/LLMs to develop scalable optimization solutions for complex high-performance computing hardware components.

Skills

Physical Design Static Timing Analysis Logic Synthesis Floorplanning Clock-tree Synthesis Routing ECO RTL Python Tcl Perl Make AI Deep Learning LLMs EDA Tools

What you'll do

Drive physical design and timing for high-frequency, low-power CPUs, GPUs, LPUs, and SoCs at various levels of integration.
Manage the full implementation flow from RTL to GDSII, including synthesis, floor-planning, and equivalence checking.
Execute timing closure across multiple modes and corners while accounting for process variations, IR drop, and crosstalk.
Perform critical path planning and crafting to optimize power, performance, and area (PPA).
Develop and implement engineering change orders (ECOs) to resolve design issues during the tapeout process.
Create and manage timing constraints and perform Static Timing Analysis (STA) for blocks and full chips.
Develop scalable optimization and signoff solutions using automation or AI/Agentic frameworks.
Utilize scripting languages like Python, Tcl, or Perl to automate physical design workflows.

What we're looking for

A BS in Electrical or Computer Engineering with 5+ years of experience is required.
An MS degree with 3+ years of experience in physical design, synthesis, and timing is accepted as an alternative.
Candidates must have hands-on experience taking complex blocks or chips from RTL/netlist to tapeout.
Experience is required in logic synthesis, floorplanning, placement, clock-tree synthesis, routing, and physical optimization.
Proficiency in Static Timing Analysis (STA) and timing-constraint development across multi-mode and multi-corner environments is required.
Candidates must possess in-depth knowledge of industry-standard EDA tools.
Proficiency in scripting languages such as Python, Tcl, Perl, or Make is required.
Knowledge of AI/ML/DL/LLMs is required for this role.

Similar roles

Senior Physical Design and Timing Engineer

Nvidia

Westford, MA +1 7 days ago $168,000–$264,500

Static Timing Analysis STA Synthesis ECO RTL Floor-planning DFT Python Tcl Make Synopsys PrimeTime Cadence Tempus Physical Design

8+ yrs exp

Save

Senior ASIC Timing Engineer

Nvidia

Santa Clara, CA +3 32 days ago $136,000–$218,500

Static Timing Analysis (STA) Timing Closure Physical Design Logic Synthesis DFT Noise Analysis RTL ASIC AMS Equivalence Checking Automation

5+ yrs exp Hybrid

Save

Senior ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 37 days ago $136,000–$218,500

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture

5+ yrs exp Hybrid

Save

ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 29 days ago $116,000–$189,750

ASIC Physical Design Logic Synthesis Formal Verification Equivalence Checking RTL Timing Closure Clock Domain Crossing MTBF Analysis Synopsys Cadence Python TCL Perl Make EDA Tools Netlisting ECO Generation

Save

Senior Physical Design Engineer

Microsoft

43 days ago $119,800–$234,700

Physical Design Synthesis Place and Route Physical Verification EMIR Formal Equivalence Low Power Verification RTL Tape-out Semiconductor Design

5+ yrs exp

Save

Senior Physical Design Engineer

Samsung Semiconductor

San Jose, CA 23 days ago $138,000–$206,000

ASIC SoC RTL GDSII Synthesis Floorplanning Clock Tree Synthesis STA SDC UPF CPF DRC LVS Tcl Python Perl FinFET NoC AI/ML

5+ yrs exp

Save