GPU Physical Design Engineer

Apple Inc

Confirmed live yesterday High trust

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Work type
On-site
Location
Austin, TX
Posted
1 day ago
Freshness
Confirmed live yesterday

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How this pay compares to similar roles

Similar $210k
$137k most similar roles pay here $277k

This listing doesn't post a salary. Most similar roles pay $177,250–$241,750.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · GPU Physical Design Engineer

As a GPU Physical Design Engineer, you will work closely with the front-end team to understand chip architecture and drive physical aspects early in the design cycle. You will be responsible for developing best-in-class construction and optimization recipes for performance, power, and area on cutting-edge designs at the latest technological nodes. Your daily responsibilities include driving methodologies to streamline physical design work, supervising progress among place and route engineers, and resolving complex flow issues. You will manage large GPU designs exceeding 20 million gates with frequencies over 1GHz. Key technical requirements include using Cadence-Innovus for placement and routing, managing multi-voltage and power-gated designs, and utilizing scripting languages like TCL or Python to automate tasks. You will also address design for yield and manufacturability issues while integrating internal and external IP components.

What you'll do

  • Drive physical design construction and optimization recipes for performance, power, and area (PPA).
  • Execute place and route of GPU partitions using industry-standard tools like Cadence-Innovus.
  • Collaborate with front-end teams to provide IP feedback regarding timing and congestion.
  • Implement low-power design techniques including clock gating, power gating, and multi-voltage strategies.
  • Manage hierarchical designs and floor planning for large-scale GPU designs exceeding 20 million gates.
  • Integrate internal and external vendor IPs while defining specific physical domain requirements.
  • Develop automation scripts using TCL or Python to streamline physical design tasks and data querying.
  • Resolve complex design and flow issues related to manufacturing, yield, and physical construction.

What we're looking for

  • Bachelor's degree or foreign equivalent in Electronics Engineering, Electrical Engineering, or a related field.
  • 3 years of experience in the job offered or a related occupation.
  • Experience using industry standard automated place and route tools like Cadence-Innovus for GPU partitions.
  • Experience collaborating with FE teams to provide IP feedback regarding timing and congestion.
  • Knowledge of multi-voltage, power gated designs, and low power techniques like clock gating and custom clock construction.
  • Experience designing large GPU designs exceeding 20M gates with frequencies over 1GHz.
  • Proficiency in scripting languages such as TCL or Python to automate physical design tasks and develop utilities.
  • Experience managing hierarchical designs, integrating internal/external IP, and addressing yield and manufacturability issues.

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