Physical Design Signoff Engineer

What you'll do

• Define and own signoff criteria for static timing analysis, signal integrity, EMIR, and clock construction.
• Drive signoff reviews with design teams to assess readiness and close open items.
• Develop and maintain signoff checks, scripts, automation, and dashboards for metric tracking.
• Perform flow signoff to verify that CAD flows generate correct results.
• Debug timing and IR drop violations to ensure designs meet manufacturing and power criteria.
• Partner with PNR, CAD, Technology, and Power teams to maintain consistent methodology.
• Define implementation recipes to improve power, performance, and area (PPA) targets.

What we're looking for

• BS in Computer Science or related field.
• 10+ years of relevant industry experience.
• Proficient in programming using Python, Perl, or Tcl (preferred).
• Hands-on experience with industry PNR and timing tools such as Cadence Innovus, Synopsys ICC2 / Fusion Compiler, PrimeTime, or Tempus (preferred).
• Experience taking block-level or chip-level designs through physical implementation and signoff closure on production silicon (preferred).
• Experience in timing closure, signal integrity, low-power design techniques, and clock-tree construction (preferred).
• Excellent communication skills and ability to collaborate across design, CAD, and technology teams (preferred).
• Understanding of tradeoffs to meet PPA targets and experience defining implementation recipes to improve PPA (preferred).