Physical Design Engineer

What you'll do

• Architect macro and design module placement to optimize PPA during the floorplan stage.
• Utilize EDA tools to optimize the placement of millions of cells within the design.
• Construct clock trees to support high-performance and low-power designs.
• Route the design according to the latest technology foundry guidelines and rules.
• Perform static analysis and generate ECOs to fix timing violations on failing paths.
• Verify and resolve electrical rule checks, DRC, electromigration, and IR drop issues.
• Develop Tcl and Shell scripts to automate PnR flows and create CAD utilities.

What we're looking for

• Bachelor's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
• Experience or education in using industry standard tools for PnR implementation.
• Experience performing STA across multiple corners and modes, including fixing setup/hold violations and debugging timing paths.
• Ability to create block-level floorplans including macro placement, pin assignment, power grid design, tap cell insertion, and congestion reduction.
• Proficiency in running and debugging DRC/LVS using tools.
• Fundamental understanding of clock trees, including skew, insertion delays, and impact on setup and hold timing.
• Fundamental understanding of the impact of drive strengths, vt-swapping, and buffering on STA.
• Ability to implement power and functional changes while utilizing Tcl and Shell scripting to automate PnR flows or create CAD utilities.