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EDA tools CMOS digital design principles standard cells DFT Scan MBIST LBIST RTL2GDSII physical design flow development +4 more Show less

EDA tools CMOS digital design principles Standard cells DFT Scan MBIST LBIST Physical design flows +3 more Show less

C++ VLSI Python Perl Tcl ICC2 Innovus PrimeTime Tempus StarRC Reinforcement Learning GNNs Graph Neural Networks CI/CD +9 more Show less

C++ Python ICCAD tools Innovus Computational geometry Graph theory Algorithm development Multithreading Distributed computing High performance software design GUI development Machine learning VLSI Physical Design +8 more Show less

Tcl Python Perl Cadence Synopsys ASIC STA SDC On-Chip_Variation Signal_Integrity IR-drop_aware_STA MMMC_Analysis ECOs RTL Physical_Design DFT Power_Performance_Area_Tradeoffs EDA_Tools +13 more Show less

Perl TCL Make Python RTL Logic Synthesis Equivalence Checking Clock Domain Crossing Checks MTBF Analysis Static Timing Analysis Timing Constraints Management EDA Tools DFT Timing Closure AI Utilization +9 more Show less

Perl TCL Make Python Synopsys Cadence Logic Synthesis Equivalence Checking Formal Verification Clock Domain Crossing Checks MTBF Analysis RTL Design EDA Tools AI Utilization +9 more Show less

Python Tcl Perl Hierarchical_design_planning Power_grid_design Structured_clocks Top_level_pipeline_placement Custom_routes Bump_planning RDL_routes Multi_voltage_domain_designs DRC LVS EMIR Chiplet SerDes HBM DDR Switch_Fabric Arbiter +15 more Show less

Virtuoso RTL to GDS Flow Verilog SystemVerilog Python Perl TCL UVM DVFlow PrimeTime PTPX ICC Calibre Sonata QCAT Qualcomm SNAP Linux Git JIRA Confluence +15 more Show less

C C++ Python Perl Verilog VHDL UVM SystemC DVFlow CI/CD Linux +6 more Show less

Synopsys_Fusion_Compiler Synopsys_ICC2 Cadence_Genus Cadence_Innovus Python Perl TCL Shell_Scripting Timing_Analysis Physical_Design Clock_Tree_Synthesis Power_Optimization Logic_Optimization ASIC_Physical_Design CI/CD +10 more Show less

TCL Perl Python Prime-time Tempus ICC2 Innovus STA AOCV POCV CTS ASIC Cross-talk noise Signal Integrity Layout Parasitic Extraction +10 more Show less

Virtuoso RTL to GDS Flow Verilog SystemVerilog Python Perl TCL UVM DVFlow PrimeTime PT PowerAware ICC/Innovus Calibre Synopsys DC Cadence Genus ModelSim/QuestaSim Linux Git JIRA Confluence +15 more Show less

Python Tcl Perl DV DRC LVS EMIR bump_planning RDL_routes multi_voltage_domain_design hierarchical_design_planning power_grid_design structured_clocks top_level_pipeline_placement custom_routes package_team_collaboration design_teams_collaboration methodology_teams_collaboration +13 more Show less

Innovus ICC2 PrimeTime Calibre Pegasus ICV TCL Python Perl SDC UPF CPF CLP SerDes DDR PCIe FinFET EM/IR Thermal-aware clocking Reliability modeling RTL-to-GDS Flow Virtuoso +17 more Show less