Physical Design Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 1 day ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $205k

$137k most similar roles pay here $274k

This listing doesn't post a salary. Most similar roles pay $168,500–$241,750.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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As a Physical Design Engineer, you will collaborate with architecture, CAD, timing, and logic design teams to deliver high-quality designs. You will manage the full netlist to GDS2 implementation for partitions, ensuring all goals are met within the schedule. Your daily responsibilities include performing physical and electrical verification, driving signoff closure, and optimizing placement for millions of cells. You will construct clock trees for high performance and low power, route designs according to foundry guidelines, and resolve flow issues through script development. The role requires expertise in industry-standard PnR tools, STA across multiple corners, and DRC/LVS verification. You will also perform ECOs, manage power leakage recovery, and utilize TCL and Shell Scripting to automate flows. This role focuses on solving complex physical design challenges for SoC design partitions.

What does a Physical Design Engineer earn?

Median $179650 from 40 postings across 9 companies.

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Skills

Physical Design PnR STA DRC LVS TCL Shell Scripting Power Grid Design IR Drop Electromigration

What you'll do

Execute netlist to GDSII implementation for specific partitions while meeting schedule and design goals.
Perform timing, physical, and electrical verification to drive signoff closure for the partition.
Optimize placement of millions of cells using EDA tools to achieve best PPA results.
Construct and optimize clock trees to support high performance and low power requirements.
Route designs according to latest technology foundry guidelines and rules.
Perform static analysis and generate ECOs to fix timing, setup, and hold violations.
Resolve electrical rule violations including electromigration and IR drop issues.
Develop scripts and programs in TCL or Shell to automate PnR flows and CAD utilities.

What we're looking for

Bachelor's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field.
Experience using industry standard tools for PnR to implement and signoff SoC design partitions.
Experience using industry standard timing tools to perform STA across multiple corners and modes while fixing setup and hold violations.
Ability to create block-level floorplans including macro placement, pin assignment, power grid design, tap cell insertion, and congestion reduction.
Ability to run and debug DRC and LVS using tools to complete PV signoff and ensure designs meet foundry DRM specs.
Experience generating and analyzing clock trees while reducing skew and jitter and optimizing buffer insertion for CTS and performance.
Experience performing manual and tool-driven ECOs for timing, including buffer insertion and cell sizing, for final STA signoff.
Proficiency in TCL and Shell Scripting to automate PnR flows, parse reports, or create CAD utilities.