Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

20 of up to 20 (filtered)

Senior Physical Design Methodology Engineer, Innovus Flows

Nvidia

Remote (Santa Clara, CA) +1 5 days ago $168,000–$264,500
Actively hiring Confirmed live today Posted this week High trust Above market
Physical Design EDA Tools PPA TCL Python C++ Perl Cadence Innovus Genus Tempus Quantus Joules STA UPF FSDB SAIF PyTorch NumPy SciPy scikit-learn ML AI Synthesis DFT
7+ yrs exp Remote

Senior Physical Design Engineer

Microsoft

7 days ago $119,800–$234,700
Actively hiring Confirmed live yesterday Posted this week High trust Competitive pay
Physical Design Synthesis Place and Route Timing Signoff Physical Verification EMIR Formal Equivalence Low Power Verification Clock Construction CTS RTL to GDS PPA Semiconductor Design Tape-out Floorplanning Extraction
5+ yrs exp Hybrid

Senior Physical Design Engineer

Nvidia

Westford, MA 7 days ago $136,000–$218,500
Actively hiring Confirmed live today Posted this week High trust Competitive pay
VLSI Physical Design RTL2GDS Place and Route Timing Closure Power and Clock Distribution Physical Verification IR Drop Analysis RC Extraction Synopsys (ICC2 Cadence (Genus Python Perl Tcl Make ML AI
5+ yrs exp

Senior Physical Design and Timing Engineer

Nvidia

Westford, MA 7 days ago $168,000–$264,500
Actively hiring Confirmed live today Posted this week High trust Above market
Static Timing Analysis (STA) Synthesis ECO Physical Design RTL Python Tcl Make Synopsys PrimeTime Cadence Tempus Logical Equivalence Checking (LEC) DFT Floor-planning Routing Noise Analysis
8+ yrs exp

Senior DTCO Engineer, CPU Physical Design

Nvidia

Santa Clara, CA +3 8 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
CPU Physical Design DTCO Synthesis Place-and-Route Static Timing Analysis PPA Python Tcl Perl timing-closure Silicon Design AI Tools Hardware Design Pathfinding
5+ yrs exp

Senior ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 11 days ago $136,000–$218,500
Actively hiring Confirmed live today High trust Competitive pay
ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation
5+ yrs exp Hybrid

Senior Staff Engineer, Physical Design

Samsung Electronics

Austin, TX 15 days ago $180,200–$270,400
Actively hiring Confirmed live today Trusted Above market
GPU Physical Design SoC Design Synthesis place-and-route Clock Tree Synthesis Timing Closure Signoff STA DRC LVS Python Tcl Shell Perl ICC2 Fusion Compiler Innovus PrimeTime Tempus StarRC DTCO
10+ yrs exp

Senior Staff Engineer, Physical Design (Floorplanning)

Samsung Electronics

Austin, TX 15 days ago $180,200–$270,400
Actively hiring Confirmed live today Trusted Above market
GPU Physical Design Place-and-Route Floorplanning Timing Closure STA Power-Grid Design DRC LVS FusionCompiler Innovus ICC2 PrimeTime Tempus StarRC RedHawk Python Tcl Shell Perl DTCO PPA Physical Verification Clock Tree Synthesis Synthesis
10+ yrs exp

Senior Physical Design Engineer

Nvidia

Santa Clara, CA +1 18 days ago $168,000–$264,500
Actively hiring Confirmed live today High trust Above market
VLSI Physical Design P&R Timing Closure Static Timing Analysis IR Drop Analysis Physical Verification RC Extraction Python Perl Tcl Make Synopsys (ICC2 Cadence (Innovus Mentor Graphics ASIC Power Distribution Clock Distribution
8+ yrs exp

Senior Physical Design Interposer Engineer

Nvidia

Remote (Santa Clara, CA) +1 25 days ago $168,000–$264,500
Actively hiring Confirmed live yesterday High trust Above market
VLSI Python C++ EDA AI ML LLMs Interposer Design Signal Integrity Power Delivery Parasitic Extraction IC Physical Design Data Structures Algorithms Object-Oriented Design
8+ yrs exp Remote

Senior Physical Design and Timing Engineer

Nvidia

Santa Clara, CA +3 28 days ago $136,000–$218,500
Actively hiring Confirmed live today Trusted Competitive pay
Physical Design Static Timing Analysis Logic Synthesis Floorplanning clock-tree synthesis Routing ECO RTL Python Tcl Perl Make AI ML DL LLMs EDA Tools Signoff IR Drop Xtalk
5+ yrs exp Hybrid

Senior Physical Design Engineer

Microsoft

39 days ago $119,800–$234,700
Actively hiring Confirmed live today Low trust Competitive pay
Physical Design Synthesis Place and Route Timing Signoff Physical Verification EMIR Formal Equivalence Low Power Verification Clock Construction CTS RTL to GDS PPA Semiconductor Design Tape-out Floorplanning Extraction
5+ yrs exp Hybrid

Senior SOC Physical Design Engineer

Qualcomm

San Diego, CA 40 days ago $131,175–$173,400
Actively hiring Confirmed live today High trust Below market
Physical Design Flow SoC Floor Planning Clock Tree Synthesis Place and Route PDN Timing Analysis LVS DRC DDR Micro-architecture Algorithm Design Modeling Tapeout

Physical Design Engineer- senior

Qualcomm

Austin, TX 40 days ago $121,800–$182,600
Actively hiring Confirmed live yesterday Trusted Below market
ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting
2+ yrs exp

Senior Physical Design Methodology Engineer, PPA Fusion Compiler

Nvidia

Santa Clara, CA +2 56 days ago
Actively hiring Confirmed live yesterday Trusted
Physical Design PPA Place and Route Timing Analysis EM Noise Analysis Back-end Verification Floor planning Clock Distribution Power Distribution Scripting Design for Yield Manufacturability Thermal Management
10+ yrs exp

Senior Engineer, Physical Design AI/ML

Samsung Semiconductor

San Jose, CA 57 days ago $138,000–$206,000
Actively hiring Confirmed live today High trust Competitive pay
Machine Learning Python C++ PyTorch TensorFlow Physical Design RTL Synthesis Place and Route Clock Tree Synthesis EDA Tools PDK Generation DRC LVS Bayesian Optimization Active Learning LangGraph CrewAI Generative AI DTCO Standard Cell Architecture

Senior Physical Design Engineer

Samsung Semiconductor

San Jose, CA 69 days ago $138,000–$206,000
Actively hiring Confirmed live today Trusted Below market
VLSI ASIC SoC Physical Design RTL Synthesis Floorplanning place-and-route Clock Tree Synthesis Static Timing Analysis STA SDC IR-drop Electromigration DRC LVS FinFET Tcl Python Perl Synopsys Fusion Compiler ICC2 PrimeTime StarRC Cadence Innovus UPF CPF NoC AI/ML
5+ yrs exp

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 78 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
Physical Design ASIC Design Flow Synthesis Timing Analysis Verilog RTL Design DFT ECO Floor-planning High-Frequency Design Micro-architecture
5+ yrs exp

Senior Physical Design Engineer

Nvidia

Santa Clara, CA 84 days ago $168,000–$264,500
Actively hiring Confirmed live today Trusted Above market
Physical Design Timing Closure RC Extraction Cross talk IR drop EM analysis DRC ERC LVS Antenna checks Formal Verification Synopsys Cadence Place and Route Scan Insertion DFT Netlist GDS Timing ECO’s
6+ yrs exp

Senior Software R&D Engineer, VLSI Physical Design

Nvidia

Santa Clara, CA +1 97 days ago $168,000–$264,500
Actively hiring Confirmed live today High trust Above market
C++ VLSI Physical Design Machine Learning Python Perl Tcl ICC2 Innovus PrimeTime Tempus StarRC Distributed Computing Multithreading Reinforcement Learning GNNs EDA Tools
6+ yrs exp Hybrid