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Static Timing Analysis STA Synthesis ECO RTL Floor-planning DFT Python Tcl Make Synopsys PrimeTime Cadence Tempus Physical Design +8 more Show less

Machine Learning Deep Learning Python C++ PyTorch TensorFlow EDA Tools RTL Synthesis Place and Route Clock Tree Synthesis Bayesian Optimization Active Learning LangGraph CrewAI Generative AI PDK Generation DRC LVS +13 more Show less

ASIC SoC RTL GDSII Synthesis Floorplanning Clock Tree Synthesis STA SDC UPF CPF DRC LVS Tcl Python Perl FinFET NoC AI/ML +14 more Show less

Physical Design Synthesis Timing Analysis Floor-planning Verilog ASIC Design Flow RTL Design Verification DFT ECO High-frequency Design Micro-architecture +7 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture +9 more Show less

Physical Design Synthesis Place and Route Physical Verification EMIR Formal Equivalence Low Power Verification RTL Tape-out Semiconductor Design +5 more Show less

ASIC Physical Design Floor Planning Synthesis Verilog TCL Perl Python Shell GPU Architecture Timing Constraints Netlist +7 more Show less

C++ VLSI Physical Design EDA Tools Machine Learning Graph Neural Networks Python Tcl Perl multithreading Distributed Computing ICC2 Innovus PrimeTime Tempus StarRC +10 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Scripting Verification Validation SoC IC Package +6 more Show less

Physical Design Static Timing Analysis Logic Synthesis Floorplanning Clock-tree Synthesis Routing ECO RTL Python Tcl Perl Make AI Deep Learning LLMs EDA Tools +11 more Show less

C++ VLSI Physical Design Computational Geometry Graph Theory Machine Learning ICC2 Innovus Multithreading Distributed Computing Algorithm Development C++17 C++14 +7 more Show less