Senior Software R&D Engineer, VLSI Physical Design

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CAAustin, TX
Salary
$168,000–$264,500 / yr
Posted
51 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $216k
$138k most similar roles pay here $278k

This role pays more than 76% of similar roles. Most pay $172,000–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Software R&D Engineer, VLSI Physical Design

As a Senior Software R&D Engineer, VLSI Physical Design, you will join a team developing internal EDA tools by fusing parallel computing, machine learning, and specialized algorithms for advanced hardware designs. You will invent new optimization engines to co-optimize processes like legalization and sizing to increase chip frequency while minimizing power consumption. Your daily work involves improving C++ algorithms for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction. The role requires expertise in VLSI timing optimization, including cell libraries, interconnect models, crosstalk, glitches, IR drop, and timing constraints. You will utilize tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC, while utilizing Perl, Tcl, and Python for design flows. Advanced skills include multithreading, distributed computing, reinforcement learning, and Graph Neural Networks applied to physical design.

What you'll do

  • Invent new optimization engines that fuse independent processes like legalization and sizing to improve chip frequency and power.
  • Develop and optimize C++ algorithms for gate-level sizing, buffering, clock skew, and cell legalization.
  • Improve software for power minimization, ECO routing, and incremental parasitic extraction.
  • Design high-performance software utilizing multithreading, distributed computing, and efficient memory management.
  • Integrate machine learning frameworks, such as GNNs or reinforcement learning, into physical design workflows.
  • Own the full development lifecycle from initial discovery and invention to final deployment within design teams.
  • Enhance internal EDA tools to outperform industry alternatives in high-capacity timing closure.

What we're looking for

  • Bachelor's, Master's, PhD, or equivalent experience in Electrical Engineering or Computer Science.
  • 6+ years of experience in VLSI algorithms development using C++.
  • Strong understanding of VLSI timing optimization and related concepts like cell libraries, interconnect models, and IR drop.
  • Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC.
  • Proficiency in scripting languages including Perl, Tcl, and Python.
  • Experience in high performance software design including multithreading, distributed computing, and efficient memory/IO use.
  • Experience with C++14 or newer features such as lambdas and concurrency.
  • Experience with machine learning frameworks like reinforcement learning and Graph Neural Networks applied to physical design.

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