Senior Software R&D Engineer, VLSI Physical Design

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TX
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 97 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $216k

$135k $278k

below market most similar roles pay here above market

This role pays more than 79% of similar roles. Most pay $166,175–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Software R&D Engineer, VLSI Physical Design

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The Senior Software R&D Engineer, VLSI Physical Design joins a team developing internal EDA tools by fusing parallel computing, machine learning, and specialized algorithms. You will invent new optimization engines that co-optimize independent processes like legalization and sizing to increase chip frequency while minimizing power consumption. Daily responsibilities include improving C++ algorithms for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction. You will own the entire process from discovery to deployment, working directly with design teams. Required skills include C++, VLSI timing optimization, and familiarity with tools like ICC2, Innovus, PrimeTime, Tempus, and StarRC, along with Perl, Tcl, and Python. The role addresses high-capacity timing closure and PPA improvements for advanced AI hardware designs.

Skills

C++ VLSI Physical Design Machine Learning Python Perl Tcl ICC2 Innovus PrimeTime Tempus StarRC Distributed Computing Multithreading Reinforcement Learning GNNs EDA Tools

What you'll do

Invent new optimization engines that fuse independent processes like legalization and sizing.
Improve C++ algorithms for gate-level sizing, buffering, clock skew, and cell legalization.
Develop software for power minimization, ECO routing, and incremental parasitic extraction.
Own the full development process from initial discovery and invention to final deployment.
Work directly with design teams to facilitate the deployment of new optimization tools.
Optimize software for high-capacity timing closure to increase chip frequency and minimize power.
Implement high-performance software features including multithreading and distributed computing.

What we're looking for

BS, MS, PhD or equivalent experience in Electrical Engineering or Computer Science.
6+ years in VLSI algorithms development using C++.
Strong understanding of VLSI timing optimization, cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, and congestion.
Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC.
Proficiency in design flows written in Perl, Tcl, and Python.
Strong communication and interpersonal skills.
Experience with C++14 or newer, including lambdas and concurrency (preferred).
Experience in high performance software design including multithreading, distributed computing, and efficient memory and I/O use (preferred).